Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual de usuario Pagina 127
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Address Name Bit Description HW
Reset
Value
Access
LT VPre ovrd
Enable, Lane
0
[29] When set to 1, enables the override value for the
VPRERULE parameter stored in the LT VPre
ovrd, Lane 0 register field.
1 for
simula
tion; 0
for
compil
ation
RW
0xE0 Register 0xD3 refers to Lane 0. This register, register 0xE0, is the equivalent of
register 0xD3 for Lane 1 link training.
RW
0xE1 Register 0xD4 refers to Lane 0. This register, register 0xE1, is the equivalent of
register 0xD4 for Lane 1 link training.
RW
0xE2 Register 0xD5 refers to Lane 0. This register, register 0xE2, is the equivalent of
register 0xD5 for Lane 1 link training.
RO
0xE3 Register 0xD6 refers to Lane 0. This register, register 0xE3, is the equivalent of
register 0xD6 for Lane 1 link training..
RW
0xE4 This register is the equivalent of register 0xD3 for Lane 2 link training. RW
0xE5 This register is the equivalent of register 0xD4 for Lane 2 link training. R / RW
0xE6 This register is the equivalent of register 0xD5 for Lane 2 link training. RO
0xE7 This register is the equivalent of register 0xD6 for Lane 2 link training. RW
0xE8 This register is the equivalent of register 0xD3 for Lane 3 link training. RW
0xE9 This register is the equivalent of register 0xD4 for Lane 3 link training. R / RW
0xEA This register is the equivalent of register 0xD5 for Lane 3 link training. RO
0xEB This register is the equivalent of register 0xD6 for Lane 3 link training. RW
Related Information
Altera Transceiver PHY IP Core User Guide
The 40GBASE-KR4 variations of the 40-100GbE IP core use the 10GBASE-KR PHY IP core PHY registers
at internal offsets 0xB0–0xFF (at IP core register map offsets 0xB0–0xFF), in addition to the registers
listed in this section. Information about this PHY IP core, including register descriptions, is available in
the Backplane Ethernet 10GBASE-KR PHY IP Core with FEC Option chapter of the Altera Transceiver
PHY IP Core User Guide..
3-82
LL 40GBASE-KR4 Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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