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Parameter Name Type Required Description
SYSTOLIC_DELAY3 String No Specifies the clock source for the systolic
register inputs of the third multiplier. Values
are UNREGISTERED, CLOCK0, CLOCK1, and
CLOCK2. The value must be set similar to the
value of OUTPUT_REGISTER or set as
UNREGISTERED.
SYSTOLIC_ACLR1 String No Specifies the asynchronous clear source for
the systolic register inputs of the first
multiplier. Values are NONE, ACLR0 and
ACLR1. If omitted, the default value is NONE.
The value must be set similar to the value of
OUTPUT_ACLR.
SYSTOLIC_ACLR3 String No Specifies the asynchronous clear source for
the systolic register inputs of the third
multiplier. Values are NONE, ACLR0 and
ACLR1. If omitted, the default value is NONE.
The value must be set similar to the value of
OUTPUT_ACLR.
COEF0_[] Integer No Specifies the coefficient value [0…7] for the
inputs of the first multiplier. The number of
coefficient bits must be set similar to the
value of WIDTH_COEF.
COEF1_[] Integer No Specifies the coefficient value [0…7] for the
inputs of the second multiplier. The number
of coefficient bits must be set similar to the
value of WIDTH_COEF.
COEF2_[] Integer No Specifies the coefficient value [0…7] for the
inputs of the third multiplier. The number
of coefficient bits must be set similar to the
value of WIDTH_COEF.
COEF3_[] Integer No Specifies the coefficient value [0…7] for the
inputs of the fourth multiplier. The number
of coefficient bits must be set similar to the
value of WIDTH_COEF.
DOUBLE_ACCUMULATOR String No Enables the double accumulator register.
Values are YES and NO. This parameter is
only available for family Arria V.
INPUT_A[0…3]_LATENCY_CLOCK String No Specifies the clock signal for the pipeline
register on the corresponding dataa[] port.
Values are UNREGISTERED, CLOCK0, CLOCK1,
and CLOCK2. If omitted, the default value is
UNREGISTERED.
INPUT_A[0…3]_LATENCY_ACLR String No Specifies the asynchronous clear signal for
the pipeline register on the corresponding
dataa[] port. Values are NONE, ACLR0,
ACLR1. If omitted, the default value is NONE.
UG-01063
2014.12.19
ALTERA_MULT_ADD Parameters
6-17
ALTERA_MULT_ADD (Multiply-Adder)
Altera Corporation
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- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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