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Integer Arithmetic Megafunctions
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2014.12.19
UG-01063
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You can use Altera
®
integer megafunction IP cores to perform mathematical operations in your design.
These functions offer more efficient logic synthesis and device implementation than coding your own
functions. You can customize the IP cores to accommodate your design requirements.
Altera integer arithmetic megafunctions are divided into the following two categories:
• Library of parameterized modules (LPM) IP cores
• Altera-specific (ALT) IP cores
The following table lists the integer arithmetic IP cores.
Table 1-1: List of IP Cores
IP Cores Function Overview
LPM Megafunctions
LPM_COUNTER (Counter) Counter
LPM_DIVIDE (Divider) Divider
LPM_MULT (Multiplier) Multiplier
Altera-specific (ALT) Megafunctions
ALTECC ECC Encoder/Decoder
ALTERA_MULT_ADD (Multiply-Adder) Multiplier-Adder
ALTMEMMULT (Memory-based Constant
Coefficient Multiplier)
Memory-based Constant Coefficient Multiplier
ALTMULT_ACCUM (Multiply-Accumulate) Multiplier-Accumulator
ALTERA_MULT_ADD (Multiply-Adder) Multiplier-Adder
ALTMULT_COMPLEX (Complex Multiplier) Complex Multiplier
ALTSQRT (Integer Square Root) Integer Square-Root
PARALLEL_ADD (Parallel Adder) Parallel Adder
If you are unfamiliar with IP cores, refer to the Introduction to IP Cores User Guide.
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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