Altera Integer Arithmetic IP Manual de usuario descargar pdf (Pagina 112)

The following figure shows the double accumulator implementation.

Figure 9-12: Double Accumulator

Mult0

Mult1

Accumulator feedba ck

Output result

+/-

Double Accu mulator Register

Output Register

Resource Utilization and Performance

The following table provides resource utilization and performance information for the ALTMULT_ADD

megafunction.

Table 9-1: ALTMULT_ADD Resource Utilization and Performance

Device family

Input data

width

Output

latency

Logic Usage

18-bit DSP f

MAX

(MHz)

(6)

Adaptive

Look-Up

Table

(ALUT)

Dedicated

Logic

(DLR)

Adaptive

Logic

Module

(ALM)

Stratix III 16 x 16 3 0 0 0 2 645

32 x 32 3 0 0 0 4 454

64 x 64 3 217 128 146 16 145

Verilog HDL Prototype

To view the Verilog HDL prototype for the megafunction, refer to the Verilog Design File (.v) altera_mf.v

in the <Quartus II installation directory>\eda\synthesis directory.

VHDL Component Declaration

(6)

The performance of the megafunction is dependant on the value of the maximum allowable ceiling f

MAX

that the selected device can achieve. Therefore, results may vary from the numbers stated in this column.

UG-01063

2014.12.19

Resource Utilization and Performance

9-11

ALTMULT_ADD (Multiply-Adder)

Altera Corporation

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