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Parameter Name Type Required Description
DSP_BLOCK_BALANCING String No Specifies whether to use a dedicated
multiplier circuitry implementation.
Values are UNUSED, AUTO, DSP BLOCKS, and
LOGIC ELEMENTS. If omitted, the default
value is UNUSED. This parameter is available
for all Altera devices except Cyclone,
HardCopy, MAX II, MAX 3000, and MAX
7000 devices.
LOGIC_ELEMENTS String No Specifies whether to use a logic element
implementation based on the selected
device family. When implemented in LEs,
the LPM_MULT megafunction uses a
variation on the Booth algorithm for all
device families. Values are OFF, SIMPLE
18-BIT MULTIPLIERS, SIMPLE
MULTIPLIERS, WIDTH 18-BIT
MULTIPLIERS, and LOGIC ELEMENTS.
DEDICATED_MULTIPLIER_
MIN_INPUT_WIDTH_FOR_AUTO
Integer No Altera-specific parameter. You must use
the LPM_HINT parameter to specify the
DEDICATED_MULTIPLIER_MIN_
OUTPUT_WIDTH_FOR_AUTO parameter in
VHDL design files. If the DEDICATED_
MULTIPLIER_CIRCUITRY parameter setting
is AUTO, this parameter specifies the
minimum value of the sum of the LPM_
WIDTHA and LPM_WIDTHB parameters in
order for the multiplier to be built using
dedicated circuitry.
INPUT_A_FIXED_VALUE String No Specifies the value for the dataa[] port.
This parameter is used when the INPUT_A_
IS_CONSTANT parameter is set to FIXED.
For example, to pass a four bit value of 3 to
the dataa[] port, the INPUT_A_FIXED_
VALUE parameter must be set to B0011.
INPUT_B_FIXED_VALUE String No Specifies the value for the datab[] port.
This parameter is used when the INPUT_B_
IS_CONSTANT parameter is set to FIXED.
For example, to pass a four bit value of 3 to
the datab[] port, the INPUT_B_FIXED_
VALUE parameter must be set to B0011.
UG-01063
2014.12.19
LPM_MULT Parameters
4-7
LPM_MULT (Multiplier)
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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