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Parameter Name Type Required Description
INPUT_SOURCE_A[0…3] String No Specifies the data source to the first
multiplier. Values are DATAA and SCANA. If
this parameter is set to DATAA, the adder uses
the values from the dataa[] port. If this
parameter is set to SCANA, the adder uses
values from the scanina[]. If omitted, the
default value is DATAA.
REPRESENTATION_A String No Specifies the numerical representation of the
multiplier input A. Values are UNSIGNED and
SIGNED. When this parameter is set to
SIGNED, the adder interprets the multiplier
input A as a signed number. When this
parameter is set to UNSIGNED, the adder
interprets the multiplier input A as an
unsigned number. If omitted, the default
value is UNSIGNED. If the corresponding
PORT_SIGNA value is USED, this parameter is
ignored. Use the parameter PORT_SIGNA to
access the signa input port for dynamic
control of the representation through the
signa input port.
REPRESENTATION_B
String No Specifies the numerical representation of the
multiplier input B. Values are UNSIGNED and
SIGNED. When this parameter is set to
SIGNED, the adder interprets the multiplier
input B as a signed number. When this
parameter is set to UNSIGNED, the adder
interprets the multiplier input B as an
unsigned number. If omitted, the default
value is UNSIGNED. If the corresponding
PORT_SIGNB value is USED, this parameter is
ignored. Use the parameter PORT_SIGNB to
access the signb input port for dynamic
control of the representation through the
signb input port.
SIGNED_REGISTER_[]
String No Parameter [A, B]. Specifies the clock signal
for the first register on the corresponding
sign[] port. Values are UNREGISTERED,
CLOCK0, CLOCK1, and CLOCK2. If the
corresponding sign[] port value is UNUSED,
this parameter is ignored. If omitted, the
default value is UNREGISTERED. The value
must be set similar to the value of INPUT_
REGISTER_A0 or set as UNREGISTERED.
UG-01063
2014.12.19
ALTERA_MULT_ADD Parameters
6-13
ALTERA_MULT_ADD (Multiply-Adder)
Altera Corporation
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- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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