Altera Arria V SoC Development Board Manual de usuario descargar pdf (Pagina 59)

Chapter 2: Board Components 2–51

Memory

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

Synchronous Flash

The development board supports a 512-Mb CFI-compatible synchronous flash device

for non-volatile storage of FPGA configuration data, board information, and test

application data. This device connects to the MAX V CPLD 5M2210 System Controller

for FPGA configuration in FPP and PS modes.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz

for a throughput of 832 Mbps per device. The write performance is 270 µs for a single

word buffer while the erase time is 800 ms for a 128 K array block.

Table 2–31 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the MAX V CPLD 5M2210 System Controller in terms

of I/O setting and direction.

Table 2–31. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U13)

Schematic Signal Name I/O Standard Description

FLASH_ADVN

1.8-V Address valid

FLASH_CEN0

1.8-V Chip enable

FLASH_CLK

1.8-V Clock

FLASH_OEN

1.8-V Output enable

FLASH_RDYBSYN

1.8-V Ready

FLASH_RESETN

1.8-V Reset

FLASH_WEN

1.8-V Write enable

FLASH_WPN

1.8-V Write protect

FSM_A1

1.8-V Address bus

FSM_A2

1.8-V Address bus

FSM_A3

1.8-V Address bus

FSM_A4

1.8-V Address bus

FSM_A5

1.8-V Address bus

FSM_A6

1.8-V Address bus

FSM_A7

1.8-V Address bus

FSM_A8

1.8-V Address bus

FSM_A9

1.8-V Address bus

FSM_A10

1.8-V Address bus

FSM_A11

1.8-V Address bus

FSM_A12

1.8-V Address bus

FSM_A13

1.8-V Address bus

FSM_A14

1.8-V Address bus

FSM_A15

1.8-V Address bus

FSM_A16

1.8-V Address bus

FSM_A17

1.8-V Address bus

FSM_A18

1.8-V Address bus

FSM_A19

1.8-V Address bus

FSM_A20

1.8-V Address bus

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 69 70

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Altera Arria V SoC Development Board Manual de usuario Pagina 59

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