Altera Arria V SoC Development Board Manual de usuario Pagina 34
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2–26 Chapter 2: Board Components
Components and Interfaces
Arria V SoC Development Board July 2014 Altera Corporation
Reference Manual
The Micrel KSZ9021RN PHY uses a multi-level POR bootstrap encoding scheme to
allow a small set of I/O pins (7) to set up a very large number of default settings
within the device. The related I/O pins have integrated pull-up or pull-down resistors
to configure the device. Table 2–18 lists the level encoding scheme.
10/100 Ethernet (FPGA)
The development board supports an RJ-45 10/100 base-T Ethernet using an external
Renesas uPD60620 PHY. This PHY supports EtherCAT, Ethernet IRT and DLR
features using a third party MAC IP. The PHY-to-MAC interface employs MII
connection using four data lines at 25 Mbps each for a connection speed of 100 Mbps.
The PHY uses 3.3-V power rails and requires a 25 MHz reference clock to be driven
from a dedicated oscillator. The PHY interfaces to a dual RJ-45 model with internal
magnetics that can be used for driving copper lines with Ethernet traffic.
21
ENET_HPS_TXD2
K18 3.3-V CMOS RGMII transmit data bus
22
ENET_HPS_TXD3
M18 3.3-V CMOS RGMII transmit data bus
3
MDI_HPS_N0
— 3.3-V CMOS Media dependent interface
6
MDI_HPS_N1
— 3.3-V CMOS Media dependent interface
8
MDI_HPS_N2
— 3.3-V CMOS Media dependent interface
11
MDI_HPS_N3
— 3.3-V CMOS Media dependent interface
2
MDI_HPS_P0
— 3.3-V CMOS Media dependent interface
5
MDI_HPS_P1
— 3.3-V CMOS Media dependent interface
7
MDI_HPS_P2
— 3.3-V CMOS Media dependent interface
10
MDI_HPS_P3
— 3.3-V CMOS Media dependent interface
Table 2–17. Ethernet PHY (HPS) Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board
Reference (U7)
Schematic Signal Name
Arria V SoC Pin
Number
I/O Standard Description
Table 2–18. Ethernet PHY (HPS) Bootstrap Encoding Scheme
Board Reference
(U7)
Schematic Signal Name Description Strapping Option
17
ENET_HPS_LED1_LINK
PHY address bit 0 Pulled low
15
ENET_HPS_LED2_LINK
PHY address bit 1 Pulled low
32
ENET_HPS_RXD0
Mode 0 Pulled high
31
ENET_HPS_RXD1
Mode 1 Pulled high
28
ENET_HPS_RXD2
Mode 2 Pulled high
27
ENET_HPS_RXD3
Mode 3 Pulled high
35
ENET_HPS_RX_CLK
PHY address bit 2 Pulled high
33
ENET_HPS_RX_DV
Clock enable Pulled low
41
CLK125_NDO_LED_MODE
Single LED mode Pulled high
- Reference Manual 1
- Arria V SoC Development Board 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- 1–2 Chapter 1: Overview 6
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- Featured Device: Arria V SoC 13
- FPGA Configuration 18
- Figure 2–3. JTAG Chain 19
- Note to Table 2–5: 21
- Figure 2–4. PFL Configuration 22
- Status Elements 23
- Setup Elements 24
- JTAG Chain Control DIP Switch 25
- HPS Jumpers 26
- CPU Reset Push Button 26
- MAX V Reset Push Button 26
- General User Input/Output 27
- User-Defined DIP Switch 28
- User-Defined LEDs 28
- Clock Circuitry 29
- Off-Board Input/Output Clock 30
- Components and Interfaces 31
- Single-Port RGMII 33
- Micrel KSZ9021RN 33
- 10/100 Ethernet (FPGA) 34
- LMK_SYSREF_FMC_N 41
- LMK_SYSREF_FMC_P 41
- RS-232 UART (HPS) 44
- Real-Time Clock (HPS) 45
- C Interface 46
- DDR3 SDRAM (FPGA) 47
- DDR3 SDRAM (HPS) 53
- QSPI Flash (HPS) 58
- EPCQ Flash 58
- Synchronous Flash 59
- Micro SD Flash Memory 60
- Power Supply 61
- Power Distribution System 62
- Power Measurement 63
- 3. Board Components Reference 65
- Notes to Table 3–2: 67
- CE EMI Conformity Caution 68
- Note to Table: 69
- Typographic Conventions 70
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