Altera Arria V SoC Development Board Manual de usuario descargar pdf (Pagina 51)

Chapter 2: Board Components 2–43

Memory

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

DDR3B_A13

AL18 1.5-V SSTL Class I Address bus

DDR3B_A14

AG18 1.5-V SSTL Class I Address bus

DDR3B_BA0

AE18 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

AD18 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

AC18 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

AR18 1.5-V SSTL Class I Row address select

DDR3B_CKE

AM16 1.5-V SSTL Class I Column address select

DDR3B_CLK_P

AF16

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3B_CLK_N

AE17

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3B_CSN

AL17 1.5-V SSTL Class I Chip select

DDR3B_DM2

AU12 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM3

AV10 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ16

AJ13 1.5-V SSTL Class I Data bus

DDR3B_DQ17

AH13 1.5-V SSTL Class I Data bus

DDR3B_DQ18

AP12 1.5-V SSTL Class I Data bus

DDR3B_DQ19

AW11 1.5-V SSTL Class I Data bus

DDR3B_DQ20

AW10 1.5-V SSTL Class I Data bus

DDR3B_DQ21

AM13 1.5-V SSTL Class I Data bus

DDR3B_DQ22

AE13 1.5-V SSTL Class I Data bus

DDR3B_DQ23

AE14 1.5-V SSTL Class I Data bus

DDR3B_DQ24

AW9 1.5-V SSTL Class I Data bus

DDR3B_DQ25

AV9 1.5-V SSTL Class I Data bus

DDR3B_DQ26

AP11 1.5-V SSTL Class I Data bus

DDR3B_DQ27

AD13 1.5-V SSTL Class I Data bus

DDR3B_DQ28

AC13 1.5-V SSTL Class I Data bus

DDR3B_DQ29

AL12 1.5-V SSTL Class I Data bus

DDR3B_DQ30

AG13 1.5-V SSTL Class I Data bus

DDR3B_DQ31

AF13 1.5-V SSTL Class I Data bus

DDR3B_DQS_P2

AW12

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 2

DDR3B_DQS_N2

AV12

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 2

DDR3B_DQS_P3

AU11

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 3

DDR3B_DQS_N3

AT11

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 3

DDR3B_ODT

AD19 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

AD17 1.5-V SSTL Class I Row address select

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 7)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard Description

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 69 70

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