Altera Arria V SoC Development Board Manual de usuario descargar pdf (Pagina 54)

2–46 Chapter 2: Board Components

Memory

Arria V SoC Development Board July 2014 Altera Corporation

Reference Manual

DDR3_HPS_A4

A8 1.5-V SSTL Class I Address bus

DDR3_HPS_A5

B7 1.5-V SSTL Class I Address bus

DDR3_HPS_A6

B9 1.5-V SSTL Class I Address bus

DDR3_HPS_A7

A9 1.5-V SSTL Class I Address bus

DDR3_HPS_A8

D9 1.5-V SSTL Class I Address bus

DDR3_HPS_A9

C10 1.5-V SSTL Class I Address bus

DDR3_HPS_A10

K7 1.5-V SSTL Class I Address bus

DDR3_HPS_A11

J7 1.5-V SSTL Class I Address bus

DDR3_HPS_A12

F9 1.5-V SSTL Class I Address bus

DDR3_HPS_A13

E9 1.5-V SSTL Class I Address bus

DDR3_HPS_A14

D11 1.5-V SSTL Class I Address bus

DDR3_HPS_BA0

L7 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA1

C9 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA2

D8 1.5-V SSTL Class I Bank address bus

DDR3_HPS_CASN

G9 1.5-V SSTL Class I Row address select

DDR3_HPS_CKE

R8 1.5-V SSTL Class I Column address select

DDR3_HPS_CLK_P

A11

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3_HPS_CLK_N

B10

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3_HPS_CSN

H9 1.5-V SSTL Class I Chip select

DDR3_HPS_DM4

T7 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DQ32

G1 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ33

F1 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ34

P6 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ35

L1 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ36

M2 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ37

M1 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ38

N1 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ39

R6 1.5-V SSTL Class I Data bus

DDR3_HPS_DQS_P4

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 4

DDR3_HPS_DQS_N4

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 4

DDR3_HPS_ODT

H7 1.5-V SSTL Class I On-die termination enable

DDR3_HPS_RASN

G8 1.5-V SSTL Class I Row address select

DDR3_HPS_RESETN

E3 1.5-V SSTL Class I Reset

DDR3_HPS_WEN

J8 1.5-V SSTL Class I Write enable

DDR3_HPS_ZQ01

— 1.5-V SSTL Class I ZQ impedance calibration

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard Description

1 2 ... 49 50 51 52 53 54 55 56 57 58 59 ... 69 70

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