Altera Arria 10 Avalon-MM DMA Manual de usuario Pagina 118

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ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequence
number of transmitted packets.
Transaction Layer Packet Checker—This block checks the integrity of the received TLP and generates
a request for transmission of an ACK/NAK DLLP.
TX Arbitration—This block arbitrates transactions, prioritizing in the following order:
Initialize FC Data Link Layer packet
ACK/NAK DLLP (high priority)
Update FC DLLP (high priority)
PM DLLP
Retry buffer TLP
TLP
Update FC DLLP (low priority)
ACK/NAK FC DLLP (low priority)
Physical Layer
The Physical Layer is the lowest level of the PCI Express protocol stack. It is the layer closest to the serial
link. It encodes and transmits packets across a link and accepts and decodes received packets. The
Physical Layer connects to the link through a high-speed SERDES interface running at 2.5 Gbps for Gen1
implementations, at 2.5 or 5.0 Gbps for Gen2 implementations, and at 2.5, 5.0 or 8.0 Gbps for Gen3
implementations.
The Physical Layer is responsible for the following actions:
Initializing the link
Scrambling/descrambling and 8B/10B encoding/decoding for 2.5 Gbps (Gen1), 5.0 Gbps (Gen2), or
128b/130b encoding/decoding of 8.0 Gbps (Gen3) per lane
Serializing and deserializing data
Operating the PIPE 3.0 Interface
Implementing auto speed negotiation (Gen2 and Gen3)
Transmitting and decoding the training sequence
Providing hardware autonomous speed control
Implementing auto lane reversal
9-6
Physical Layer
UG-01145_avmm_dma
2015.05.14
Altera Corporation
IP Core Architecture
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