Altera 100G Development Kit, Stratix IV GT Edition Manual de usuario Pagina 60

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2–52 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation
U39.F2 Data bus
DDR3B_DQ18
U44.J19
U39.F8 Data bus
DDR3B_DQ19
U44.J16
U39.H3 Data bus
DDR3B_DQ20
U44.G17
U39.H8 Data bus
DDR3B_DQ21
U44.H16
U39.G2 Data bus
DDR3B_DQ22
U44.H17
U39.H7 Data bus
DDR3B_DQ23
U44.F17
U39.D7 Data bus
DDR3B_DQ24
U44.L17
U39.C3 Data bus
DDR3B_DQ25
U44.N18
U39.C8 Data bus
DDR3B_DQ26
U44.K17
U39.C2 Data bus
DDR3B_DQ27
U44.T19
U39.A7 Data bus
DDR3B_DQ28
U44.K18
U39.A2 Data bus
DDR3B_DQ29
U44.R19
U39.B8 Data bus
DDR3B_DQ30
U44.K19
U39.A3 Data bus
DDR3B_DQ31
U44.M17
U38.G3 Data strobe N byte lane 0
DDR3B_DQS_N0
U44.A18
U38.F3 Data strobe P byte lane 0
DDR3B_DQS_P0
U44.A19
U38.B7 Data strobe N byte lane 1
DDR3B_DQS_N1
U44.D17
U38.C7 Data strobe P byte lane 1
DDR3B_DQS_P1
U44.E17
U39.G3 Data strobe N byte lane 2
DDR3B_DQS_N2
U44.G18
U39.F3 Data strobe P byte lane 2
DDR3B_DQS_P2
U44.H19
U39.B7 Data strobe N byte lane 3
DDR3B_DQS_N3
U44.M19
U39.C7 Data strobe P byte lane 3
DDR3B_DQS_P3
U44.N19
U39.K1, U38.K1 On-die termination
DDR3B_ODT
U44.H22
U39.J3, U38.J3 Row address select
DDR3B_RASN
U44.E20
U39.T2, U38.T2 Reset
DDR3B_RSTN
U44.A21
U39.L3, U38.L3 Write enable
DDR3B_WEN
U44.E19
DDR3C Interface
U29.N3, U28.N3 Address bus
DDR3C_A0
U44.M35
U29.P7, U28.P7 Address bus
DDR3C_A1
U44.L26
U29.P3, U28.P3 Address bus
DDR3C_A2
U44.G37
U29.N2, U28.N2 Address bus
DDR3C_A3
U44.H36
U29.P8, U28.P8 Address bus
DDR3C_A4
U44.K28
U29.P2, U28.P2 Address bus
DDR3C_A5
U44.M36
U29.R8, U28.R8 Address bus
DDR3C_A6
U44.A25
U29.R2, U28.R2 Address bus
DDR3C_A7
U44.F39
U29.T8, U28.T8 Address bus
DDR3C_A8
U44.C25
U29.R3, U28.R3 Address bus
DDR3C_A9
U44.H37
U29.L7, U28.L7 Address bus
DDR3C_A10
U44.D30
Table 2–37. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 8)
Board Reference Description
Schematic
Signal Name
Stratix IV GT
Device
Pin Name
Other
Connections
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