Altera 100G Development Kit, Stratix IV GT Edition Manual de usuario descargar pdf (Pagina 54)

2–46 Chapter 2: Board Components

Components and Interfaces

100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation

J30.E8 Transmit XCVR pair 12 from FPGA

INT_TX_N12

1.2-V

PCML

C39 —

J30.A9 Transmit XCVR pair 13 from FPGA

INT_TX_P13

D37 —

J30.B9 Transmit XCVR pair 13 from FPGA

INT_TX_N13

C37 —

J30.A3 Transmit XCVR pair 14 from FPGA

INT_TX_P14

R41 —

J30.B3 Transmit XCVR pair 14 from FPGA

INT_TX_N14

R42 —

J30.D2 Transmit XCVR pair 15 from FPGA

INT_TX_P15

AA41 —

J30.E2 Transmit XCVR pair 15 from FPGA

INT_TX_N15

AA42 —

J30.D4 Transmit XCVR pair 16 from FPGA

INT_TX_P16

N41 —

J30.E4 Transmit XCVR pair 16 from FPGA

INT_TX_N16

N42 —

J30.A5 Transmit XCVR pair 17 from FPGA

INT_TX_P17

J41 —

J30.B5 Transmit XCVR pair 17 from FPGA

INT_TX_N17

J42 —

J30.G5 Transmit XCVR pair 18 from FPGA

INT_TX_P18

L41 —

J30.H5 Transmit XCVR pair 18 from FPGA

INT_TX_N18

L42 —

J30.G3 Transmit XCVR pair 19 from FPGA

INT_TX_P19

W41 —

J30.H3 Transmit XCVR pair 19 from FPGA

INT_TX_N19

W42 —

J39.A7 Receive XCVR pair 0 to FPGA

INT_CAP_RX_P0

AH43 —

J39.B7 Receive XCVR pair 0 to FPGA

INT_CAP_RX_N0

AH44 —

J39.D6 Receive XCVR pair 1 to FPGA

INT_CAP_RX_P1

AM43 —

J39.E6 Receive XCVR pair 1 to FPGA

INT_CAP_RX_N1

AM44 —

J39.D8 Receive XCVR pair 2 to FPGA

INT_CAP_RX_P2

AF43 —

J39.E8 Receive XCVR pair 2 to FPGA

INT_CAP_RX_N2

AF44 —

J39.A9 Receive XCVR pair 3 to FPGA

INT_CAP_RX_P3

AD43 —

J39.B9 Receive XCVR pair 3 to FPGA

INT_CAP_RX_N3

AD44 —

J39.A3 Receive XCVR pair 4 to FPGA

INT_CAP_RX_P4

AY43 —

J39.B3 Receive XCVR pair 4 to FPGA

INT_CAP_RX_N4

AY44 —

J39.D2 Receive XCVR pair 5 to FPGA

INT_CAP_RX_P5

BC37 —

J39.E2 Receive XCVR pair 5 to FPGA

INT_CAP_RX_N5

BD37 —

J39.D4 Receive XCVR pair 6 from FPGA

INT_CAP_RX_P6

AV43 —

J39.E4 Receive XCVR pair 6 from FPGA

INT_CAP_RX_N6

AV44 —

J39.A5 Receive XCVR pair 7 from FPGA

INT_CAP_RX_P7

AP43 —

J39.B5 Receive XCVR pair 7 from FPGA

INT_CAP_RX_N7

AP44 —

J39.G5 Receive XCVR pair 8 from FPGA

INT_CAP_RX_P8

AT43 —

J39.H5 Receive XCVR pair 8 from FPGA

INT_CAP_RX_N8

AT44 —

J39.G3 Receive XCVR pair 9 from FPGA

INT_CAP_RX_P9

BC39 —

J39.H3 Receive XCVR pair 9 from FPGA

INT_CAP_RX_N9

BD39 —

J5.A7 Receive XCVR pair 10 from FPGA

INT_CAP_RX_P10

D43 —

J5.B7 Receive XCVR pair 10 from FPGA

INT_CAP_RX_N10

D44 —

J5.D6 Receive XCVR pair 11 from FPGA

INT_CAP_RX_P11

H43 —

Table 2–35. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Description

Schematic

Signal Name

i/O

Standard

Stratix IV GT

Device

Pin Name

Other

Connections

1 2 ... 49 50 51 52 53 54 55 56 57 58 59 ... 79 80

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