
Chapter 2: Board Components 2–37
SSRAM
September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual
U57.E10 Flash data bus bit 10
FSM_D10
2.5-V CMOS
AU9 U65.F4, U72.F8
U57.E11 Flash data bus bit 11
FSM_D11
AU8 U65.G4, U72.E7
U57.F10 Flash data bus bit 12
FSM_D12
AR7 U65.F5, U72.D8
U57.F11 Flash data bus bit 13
FSM_D13
AT8 U65.G6, U72.D5
U57.G10 Flash data bus bit 14
FSM_D14
AT6 U65.F6, U72.D6
U57.G11 Flash data bus bit 15
FSM_D15
AT7 U65.G7, U72.E6
U57.D1 Flash data bus bit 16
FSM_D16
AJ14 —
U57.D2 Flash data bus bit 17
FSM_D17
AK14 —
U57.E1 Flash data bus bit 18
FSM_D18
AT11 —
U57.E2 Flash data bus bit 19
FSM_D19
AU11 —
U57.F1 Flash data bus bit 20
FSM_D20
AM11 —
U57.F2 Flash data bus bit 21
FSM_D21
AN11 —
U57.G1 Flash data bus bit 22
FSM_D22
AM12 —
U57.G2 Flash data bus bit 23
FSM_D23
AN12 —
U57.J1 Flash data bus bit 24
FSM_D24
AH14 —
U57.J2 Flash data bus bit 25
FSM_D25
AG15 —
U57.K1 Flash data bus bit 26
FSM_D26
AR11 —
U57.K2 Flash data bus bit 27
FSM_D27
AP11 —
U57.L1 Flash data bus bit 28
FSM_D28
AT10 —
U57.L2 Flash data bus bit 29
FSM_D29
AT9 —
U57.M1 Flash data bus bit 30
FSM_D30
AN9 —
U57.M2 Flash data bus bit 31
FSM_D31
AN8 —
U57.N11 Data bus parity byte lane 0
SSRAM_DQP0
——
U57.C11 Data bus parity byte lane 1
SSRAM_DQP1
——
U57.C1 Data bus parity byte lane 2
SSRAM_DQP2
——
U57.N1 Data bus parity byte lane 3
SSRAM_DQP3
——
U57.B6 Clock
SSRAM_CLK
——
U57.B8 Output enable
SSRAM_OEn
——
U57.A3 Output enable
SSRAM_OE1n
——
U57.B3 Chip enable
SSRAM_CE2
——
U57.A6 Chip enable
SSRAM_CEn3
——
U57.R1 Mode
SSRAM_MODE
——
U57.B5 Byte lane 0 write enable
SSRAM_BWn0
——
U57.A5 Byte lane 1 write enable
SSRAM_BWn1
——
U57.A4 Byte lane 2 write enable
SSRAM_BWn2
——
U57.B4 Byte lane 3 write enable
SSRAM_BWn3
——
U57.A7 Byte write enable
SSRAM_BWEn
——
U57.B7 Global write enable
SSRAM_GWn
——
Table 2–27. SSRAM Pin-Out (Part 2 of 3)
Board
Reference
Description
Schematic
Signal Name
I/O Standard
Stratix IV GT
Device
Pin Name
Other Connections
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