Altera 100G Development Kit, Stratix IV GT Edition Manual de usuario descargar pdf (Pagina 55)

Chapter 2: Board Components 2–47

Components and Interfaces

September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual

J5.E6 Receive XCVR pair 11 from FPGA

INT_CAP_RX_N11

1.2-V

PCML

H44 —

J5.D8 Receive XCVR pair 12 from FPGA

INT_CAP_RX_P12

B40 —

J5.E8 Receive XCVR pair 12 from FPGA

INT_CAP_RX_N12

A40 —

J5.A9 Receive XCVR pair 13 from FPGA

INT_CAP_RX_P13

B38 —

J5.B9 Receive XCVR pair 13 from FPGA

INT_CAP_RX_N13

A38 —

J5.A3 Receive XCVR pair 14 from FPGA

INT_CAP_RX_P14

T43 —

J5.B3 Receive XCVR pair 14 from FPGA

INT_CAP_RX_N14

T44 —

J5.D2 Receive XCVR pair 15 from FPGA

INT_CAP_RX_P15

AB43 —

J5.E2 Receive XCVR pair 15 from FPGA

INT_CAP_RX_N15

AB44 —

J5.D4 Receive XCVR pair 16 from FPGA

INT_CAP_RX_P16

P43 —

J5.E4 Receive XCVR pair 16 from FPGA

INT_CAP_RX_N16

P44 —

J5.A5 Receive XCVR pair 17 from FPGA

INT_CAP_RX_P17

K43 —

J5.B5 Receive XCVR pair 17 from FPGA

INT_CAP_RX_N17

K44 —

J5.G5 Receive XCVR pair 18 from FPGA

INT_CAP_RX_P18

M43 —

J5.H5 Receive XCVR pair 18 from FPGA

INT_CAP_RX_N18

M44 —

J5.G3 Receive XCVR pair 19 from FPGA

INT_CAP_RX_P19

Y43 —

J5.H3 Receive XCVR pair 19 from FPGA

INT_CAP_RX_N19

Y44 —

J39.B1

Receive clock for the first 10 bits of

the bus

INT_LSB_CON_RX_CLK_N

—J38.1

J39.A1

Receive clock for the first 10 bits of

the bus

INT_LSB_CON_RX_CLK_P

—J36.1

J39.E10

Receive flow control clock signal for

the first 10 bits of the bus

INT_LSB_CON_RX_FC_CK

LVCMOS

V32 —

J39.H7

Receive flow control data signal for

the first 10 bits of the bus

INT_LSB_CON_RX_FC_DATA

M39 —

J39.H9

Receive flow control synchronization

signal for the first 10 bits of the bus

INT_LSB_CON_RX_FC_SYNC

R38 —

J57.B1

Transmit clock for the first 10 bits of

the bus

INT_LSB_CON_TX_CLK_N

1.2-V

PCML

BB44 —

J57.A1

Transmit clock for the first 10 bits of

the bus

INT_LSB_CON_TX_CLK_P

BB43 —

J57.E10

Transmit flow control clock signal for

the first 10 bits of the bus

INT_LSB_CON_TX_FC_CK

LVCMOS

R39 —

J57.H7

Transmit flow control data signal for

the first 10 bits of the bus

INT_LSB_CON_TX_FC_DATA

N39 —

J57.H9

Transmit flow control

synchronization signal for the first

10 bits of the bus

INT_LSB_CON_TX_FC_SYNC

U32 —

Table 2–35. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Description

Schematic

Signal Name

i/O

Standard

Stratix IV GT

Device

Pin Name

Other

Connections

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 79 80

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