Altera 100G Development Kit, Stratix IV GT Edition Manual de usuario descargar pdf (Pagina 24)

2–16 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation

U72.J6

Single-ended clock input (limited to

300 MHz) in the MAX II device from

clock tree A structure.

Input

SE_CLKA_MAX

— U14.19

U72.K6

Single-ended clock input (limited to

300 MHz) in the MAX II device from

clock tree B structure.

Input

SE_CLKB_MAX

— U17.19

U72.H5

Chip select for the first current

sense ADC

Output

SENSE_CE0

— U63.4

U72.J2

Chip select for the second current

sense ADC

Output

SENSE_CE1

— U62.4

U72.G18

Status indicator for programming

the FPGA

Output

STATUSN_LED

— D41.2

U72.E15 Temperature sense clock Output

TSENSE_SMB_CLK

— U70.8

U72.C16 Temperature sense data Bidirectional

TSENSE_SMB_DATA

— U70.7

U72.K4

USB control and data interface.

Connects to the MAX II embedded

USB-Blaster to pass USB data.

Bidirectional

USB_MAX_D0

— U80.L11

U72.L2 Bidirectional

USB_MAX_D1

— U80.C11

U72.L6 Bidirectional

USB_MAX_D2

— U80.D11

U72.L3 Bidirectional

USB_MAX_D3

— U80.E11

U72.L5 Bidirectional

USB_MAX_D4

— U80.F11

U72.M1 Bidirectional

USB_MAX_D5

— U80.H11

U72.L4 Bidirectional

USB_MAX_D6

— U80.L7

U72.M2 Bidirectional

USB_MAX_D7

— U80.L8

U72.K2 Output

USB_MAX_PWR_ENn

— U80.L3

U72.L1 Output

USB_MAX_RDn

— U80.L5

U72.J5 Input

USB_MAX_RXFn

— U80.L2

U72.K3 Input

USB_MAX_TXEn

— U80.L4

U72.K5 Output

USB_MAX_WR

— U80.L6

U72.R6 User DIP switch Input

USER_DIPSW0

—SW3.1

U72.U4 User DIP switch Input

USER_DIPSW1

—SW3.2

U72.T6 User DIP switch Input

USER_DIPSW2

—SW3.3

U72.V4 User DIP switch Input

USER_DIPSW3

—SW3.4

U72.N7 User DIP switch Input

USER_DIPSW4

—SW3.5

U72.T5 User DIP switch Input

USER_DIPSW5

—SW3.6

U72.P7 User DIP switch Input

USER_DIPSW6

—SW3.7

U72.U5 User DIP switch Input

USER_DIPSW7

—SW3.8

U72.C10 User LED Output

USER_LED0

— D24.2

U72.A11 User LED Output

USER_LED1

— D23.2

U72.C9 User LED Output

USER_LED2

— D22.2

U72.B10 User LED Output

USER_LED3

— D21.2

U72.U3 User push-button Input

USER_PB0

— S4.2

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 5 of 6)

EPM2210

Pin Number

Description Type

Schematic Signal

Name

Stratix IV

GT Device

Pin Name

Other

Connections

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 79 80

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