Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manual de usuario Pagina 372
- Pagina / 783
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Mentor VIP AE AXI3/4 User Guide, V10.2b
352
VHDL AXI3 and AXI4 Slave BFMs
set_config()
September 2013
set_config()
This nonblocking procedure sets the configuration of the slave BFM.
Prototype
-- * = axi| axi4
-- ** = AXI | AXI4
procedure set_config
(
config_name : in std_logic_vector(7 downto 0);
config_val : in std_logic_vector(**_MAX_BIT_SIZE-1 downto 0)|
integer;
bfm_id : in integer;
path_id : in *_path_t; --optional
signal tr_if : inout *_vhd_if_struct_t
);
Arguments
config_name (AXI3) Configuration name:
AXI_CONFIG_SETUP_TIME
AXI_CONFIG_HOLD_TIME
AXI_CONFIG_MAX_TRANSACTION_TIME_FACTOR
AXI_CONFIG_TIMEOUT_MAX_DATA_TRANSFER
AXI_CONFIG_BURST_TIMEOUT_FACTOR
AXI_CONFIG_WRITE_CTRL_TO_DATA_MINTIME
AXI_CONFIG_MASTER_WRITE_DELAY
AXI_CONFIG_MASTER_DEFAULT_UNDER_RESET
AXI_CONFIG_SLAVE_DEFAULT_UNDER_RESET
AXI_CONFIG_ENABLE_ALL_ASSERTIONS
AXI_CONFIG_ENABLE_ASSERTION
AXI_CONFIG_MAX_LATENCY_AWVALID_ASSERTION_
TO_AWREADY
AXI_CONFIG_MAX_LATENCY_ARVALID_ASSERTION_
TO_ARREADY
AXI_CONFIG_MAX_LATENCY_RVALID_ASSERTION_
TO_RREADY
AXI_CONFIG_MAX_LATENCY_BVALID_ASSERTION_
TO_BREADY
AXI_CONFIG_MAX_LATENCY_WVALID_ASSERTION_
TO_WREADY
AXI_CONFIG_READ_DATA_REORDERING_DEPTH
AXI_CONFIG_SLAVE_START_ADDR
AXI_CONFIG_SLAVE_END_ADDR
AXI_CONFIG_MASTER_ERROR_POSITION
AXI_CONFIG_SUPPORT_EXCLUSIVE_ACCESS
AXI_CONFIG_MAX_OUTSTANDING_WR
AXI_CONFIG_MAX_OUTSTANDING_RD
- Verification IP Altera 1
- Edition 1
- AMBA AXI3/4 1
- User Guide 1
- Table of Contents 10
- List of Examples 13
- List of Figures 16
- List of Tables 17
- About This User Guide 19
- Protocol Restrictions 19
- Supported Simulators 20
- Simulator GCC Requirements 21
- Chapter 1 23
- Mentor VIP Altera Edition 23
- What Is a Transaction? 24
- An AXI Transaction 24
- Chapter 2 31
- SystemVerilog API Overview 31
- Transaction Record 33
- Table 2-1. Transaction Fields 35
- AXI3 BFM Delay Mode 48
- Chapter 3 51
- SystemVerilog Master API 57
- Chapter 4 87
- SystemVerilog Slave API 93
- Operational 100
- Transaction 100
- AXI3 Example 101
- AXI4 Example 101
- September 2013 107
- AXI3 BFM 109
- Helper Functions 118
- Chapter 5 121
- Monitor BFM Protocol Support 122
- Monitor Timing and Events 122
- Monitor BFM Configuration 122
- Timing Variables 124
- Slave Attributes 125
- Error Detection 125
- Monitor Assertions 126
- SystemVerilog Monitor API 127
- Prototype 128
- Arguments 128
- Arguments config_name 130
- (AXI4) Configuration name: 130
- Chapter 6 155
- SystemVerilog Tutorials 155
- AXI3 BFM Master Test Program 156
- AXI4 BFM Master Test Program 161
- Verifying a Slave DUT 162
- Verifying a Master DUT 173
- Example 6-30. process_write 184
- Example 6-31. handle_write 185
- AXI4 BFM Slave Test Program 186
- Internal Memory 187
- Example 6-44. handle_read 197
- Example 6-45. process_write 198
- Chapter 7 203
- VHDL API Overview 203
- Test Program VHDL 204
- VHDL to SV Wrapper 204
- Configuration 205
- Creating Transactions 206
- AXI4 Transaction Definition 207
- Table 7-1. Transaction Fields 209
- Transaction Field Description 209
- Protocol Transaction Fields 209
- Executing Transactions 212
- Waiting Events 213
- Access Transaction Record 214
- Operation Mode 216
- Channel Handshake Delay 217
- AXI4 BFM Handshake Delay 218
- Data Beat Done 220
- Transaction Done 220
- Chapter 8 221
- Master BFM Protocol Support 222
- Master Timing and Events 222
- Master BFM Configuration 222
- Master Assertions 225
- AXI4 Assertion Configuration 226
- VHDL Master API 227
- Protocol 233
- Arguments cache 255
- AXI4 BFM 297
- Chapter 9 365
- VHDL AXI3 and AXI4 Slave BFMs 365
- Slave BFM Configuration 366
- Slave Assertions 369
- AXI3 Assertion Configuration 370
- VHDL Slave API 371
- Returns transaction_id 378
- Chapter 10 505
- VHDL Monitor API 511
- Chapter 11 627
- VHDL Tutorials 627
- Example 11-29. handle read 656
- Example 11-38. process_write 668
- Chapter 12 673
- Running the Qsys Tool 676
- Running Simulation 679
- Example Script Processing 682
- Appendix A 685
- Assertions 685
- AXI4 Assertions 698
- Appendix B 715
- Programs 715
- Appendix C 751
- End-User License Agreement 779
Relacionado con productos y manuales para Instrumentos de medición Altera Mentor Verification IP Altera Edition AMBA AXI3/4T
Instrumentos de medición Altera PCI Development Kit, Cyclone II Edition Getting St Manual de usuario
(40 paginas)
(40 paginas)
Instrumentos de medición Altera PCI Express Development Kit, Stratix II GX Edition Manual de usuario
(36 paginas)
(36 paginas)
Instrumentos de medición Altera PowerPlay Early Power Estimator for Altera CPLDs Manual de usuario
(30 paginas)
(30 paginas)
Instrumentos de medición Altera QDRII SRAM Controller MegaCore Function Manual de usuario
(68 paginas)
(68 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.027 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales