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SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b
165
September 2013
The Slave BFM helper function set_read_data() then fills a complete read data bus width of
data into the Slave BFM data_words[] array. At this point a read data phase is executed on to
the read data channel if the slave_mode setting is AXI_PHASE_SLAVE, otherwise it executes a
complete read data burst only when the Slave BFM data_words[] array contains a complete
burst of read data.
Example 6-29. handle_read
// Task : handle_read
// This method reads data from memory and send read data/response
// either at burst or phase level depending upon slave working
// mode.
task automatic handle_read(input axi_transaction read_trans);
addr_t addr[];
bit [7:0] mem_data[];
set_read_data_valid_delay(read_trans);
for(int i = 0; bfm.get_read_addr(read_trans, i, addr); i++)
begin
mem_data = new[addr.size()];
for (int j = 0; j < addr.size(); j++)
mem_data[j] = do_byte_read(addr[j]);
bfm.set_read_data(read_trans, i, addr, mem_data);
if (slave_mode == AXI_PHASE_SLAVE)
bfm.execute_read_data_phase(read_trans, i);
end
if (slave_mode == AXI_TRANSACTION_SLAVE)
bfm.execute_read_data_burst(read_trans);
endtask
The processing of write transactions in the Slave Test Program works in a similar way as that
described for read transactions. Processing a write transaction requires both a process_write
task and a handle_write task.
The main difference is that the write transaction handling gets the write data burst and stores it
in the Slave Test Program internal memory depending on the slave_mode setting, adhering to
the state of the write strobes signal WSTRB. There is also an additional write response phase that
is required for the AXI3 write channel.
- Verification IP Altera 1
- Edition 1
- AMBA AXI3/4 1
- User Guide 1
- Table of Contents 10
- List of Examples 13
- List of Figures 16
- List of Tables 17
- About This User Guide 19
- Protocol Restrictions 19
- Supported Simulators 20
- Simulator GCC Requirements 21
- Chapter 1 23
- Mentor VIP Altera Edition 23
- What Is a Transaction? 24
- An AXI Transaction 24
- Chapter 2 31
- SystemVerilog API Overview 31
- Transaction Record 33
- Table 2-1. Transaction Fields 35
- AXI3 BFM Delay Mode 48
- Chapter 3 51
- SystemVerilog Master API 57
- Chapter 4 87
- SystemVerilog Slave API 93
- Operational 100
- Transaction 100
- AXI3 Example 101
- AXI4 Example 101
- September 2013 107
- AXI3 BFM 109
- Helper Functions 118
- Chapter 5 121
- Monitor BFM Protocol Support 122
- Monitor Timing and Events 122
- Monitor BFM Configuration 122
- Timing Variables 124
- Slave Attributes 125
- Error Detection 125
- Monitor Assertions 126
- SystemVerilog Monitor API 127
- Prototype 128
- Arguments 128
- Arguments config_name 130
- (AXI4) Configuration name: 130
- Chapter 6 155
- SystemVerilog Tutorials 155
- AXI3 BFM Master Test Program 156
- AXI4 BFM Master Test Program 161
- Verifying a Slave DUT 162
- Verifying a Master DUT 173
- Example 6-30. process_write 184
- Example 6-31. handle_write 185
- AXI4 BFM Slave Test Program 186
- Internal Memory 187
- Example 6-44. handle_read 197
- Example 6-45. process_write 198
- Chapter 7 203
- VHDL API Overview 203
- Test Program VHDL 204
- VHDL to SV Wrapper 204
- Configuration 205
- Creating Transactions 206
- AXI4 Transaction Definition 207
- Table 7-1. Transaction Fields 209
- Transaction Field Description 209
- Protocol Transaction Fields 209
- Executing Transactions 212
- Waiting Events 213
- Access Transaction Record 214
- Operation Mode 216
- Channel Handshake Delay 217
- AXI4 BFM Handshake Delay 218
- Data Beat Done 220
- Transaction Done 220
- Chapter 8 221
- Master BFM Protocol Support 222
- Master Timing and Events 222
- Master BFM Configuration 222
- Master Assertions 225
- AXI4 Assertion Configuration 226
- VHDL Master API 227
- Protocol 233
- Arguments cache 255
- AXI4 BFM 297
- Chapter 9 365
- VHDL AXI3 and AXI4 Slave BFMs 365
- Slave BFM Configuration 366
- Slave Assertions 369
- AXI3 Assertion Configuration 370
- VHDL Slave API 371
- Returns transaction_id 378
- Chapter 10 505
- VHDL Monitor API 511
- Chapter 11 627
- VHDL Tutorials 627
- Example 11-29. handle read 656
- Example 11-38. process_write 668
- Chapter 12 673
- Running the Qsys Tool 676
- Running Simulation 679
- Example Script Processing 682
- Appendix A 685
- Assertions 685
- AXI4 Assertions 698
- Appendix B 715
- Programs 715
- Appendix C 751
- End-User License Agreement 779
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