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VHDL AXI3 and AXI4 Master BFMs
Master BFM Configuration
Mentor VIP AE AXI3/4 User Guide, V10.2b
205
September 2013
A master BFM has configuration fields that you can set via the set_config() function to
configure timeout factors, slave exclusive support, setup and hold times, etc. You can also get
the value of a configuration field via the get_config() procedures. The full list of configuration
fields is described in Table 8-2 below.
**_RDATA_WIDTH Read data signal width in bits. This applies to the RDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.
**_WDATA_WIDTH Write data signal width in bits. This applies to the WDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.
**_ID_WIDTH ID signal width in bits. This applies to the RID and WID signals.
Refer to the AMBA AXI Protocol specification for more details.
Default: 4.
AXI4_USER_WIDTH (AXI4) User data signal width in bits. This applies to the
ARUSER, AWUSER, RUSER, WUSER and BUSER signals.
Refer to the AMBA AXI Protocol specification for more details.
Default: 8.
AXI4_REGION_MAP_SIZE (AXI4) Region signal width in bits. This applies to the
ARREGION and AWREGION signals. Refer to the AMBA AXI
Protocol specification for more details. Default: 16.
Table 8-2. Master BFM Configuration
Configuration Field Description
Timing Variables
**_CONFIG_SETUP_TIME The setup-time prior to the active edge of
ACLK, in units of simulator time-steps for all
signals.
1
Default: 0.
**_CONFIG_HOLD_TIME The hold-time after the active edge of
ACLK, in units of simulator time-steps for all
signals.
1
Default: 0.
**_CONFIG_MAX_TRANSACTION_TIME_FACTOR The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI_CONFIG_TIMEOUT_MAX_DATA_TRANSFER (AXI3) The maximum number of write data
beats that the AXI3 BFM can generate as
part of write data burst of write transfer.
Default: 1024.
**_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the individual
phases of a read/write transaction in clock
cycles. Default: 10000.
**_CONFIG_MAX_LATENCY_AWVALID_
ASSERTION_TO_AWREADY
The maximum timeout duration from the
assertion of AWVALID to the assertion of
AWREADY in clock periods (default
10000).
Table 8-1. Master BFM Signal Width Parameters
- Verification IP Altera 1
- Edition 1
- AMBA AXI3/4 1
- User Guide 1
- Table of Contents 10
- List of Examples 13
- List of Figures 16
- List of Tables 17
- About This User Guide 19
- Protocol Restrictions 19
- Supported Simulators 20
- Simulator GCC Requirements 21
- Chapter 1 23
- Mentor VIP Altera Edition 23
- What Is a Transaction? 24
- An AXI Transaction 24
- Chapter 2 31
- SystemVerilog API Overview 31
- Transaction Record 33
- Table 2-1. Transaction Fields 35
- AXI3 BFM Delay Mode 48
- Chapter 3 51
- SystemVerilog Master API 57
- Chapter 4 87
- SystemVerilog Slave API 93
- Operational 100
- Transaction 100
- AXI3 Example 101
- AXI4 Example 101
- September 2013 107
- AXI3 BFM 109
- Helper Functions 118
- Chapter 5 121
- Monitor BFM Protocol Support 122
- Monitor Timing and Events 122
- Monitor BFM Configuration 122
- Timing Variables 124
- Slave Attributes 125
- Error Detection 125
- Monitor Assertions 126
- SystemVerilog Monitor API 127
- Prototype 128
- Arguments 128
- Arguments config_name 130
- (AXI4) Configuration name: 130
- Chapter 6 155
- SystemVerilog Tutorials 155
- AXI3 BFM Master Test Program 156
- AXI4 BFM Master Test Program 161
- Verifying a Slave DUT 162
- Verifying a Master DUT 173
- Example 6-30. process_write 184
- Example 6-31. handle_write 185
- AXI4 BFM Slave Test Program 186
- Internal Memory 187
- Example 6-44. handle_read 197
- Example 6-45. process_write 198
- Chapter 7 203
- VHDL API Overview 203
- Test Program VHDL 204
- VHDL to SV Wrapper 204
- Configuration 205
- Creating Transactions 206
- AXI4 Transaction Definition 207
- Table 7-1. Transaction Fields 209
- Transaction Field Description 209
- Protocol Transaction Fields 209
- Executing Transactions 212
- Waiting Events 213
- Access Transaction Record 214
- Operation Mode 216
- Channel Handshake Delay 217
- AXI4 BFM Handshake Delay 218
- Data Beat Done 220
- Transaction Done 220
- Chapter 8 221
- Master BFM Protocol Support 222
- Master Timing and Events 222
- Master BFM Configuration 222
- Master Assertions 225
- AXI4 Assertion Configuration 226
- VHDL Master API 227
- Protocol 233
- Arguments cache 255
- AXI4 BFM 297
- Chapter 9 365
- VHDL AXI3 and AXI4 Slave BFMs 365
- Slave BFM Configuration 366
- Slave Assertions 369
- AXI3 Assertion Configuration 370
- VHDL Slave API 371
- Returns transaction_id 378
- Chapter 10 505
- VHDL Monitor API 511
- Chapter 11 627
- VHDL Tutorials 627
- Example 11-29. handle read 656
- Example 11-38. process_write 668
- Chapter 12 673
- Running the Qsys Tool 676
- Running Simulation 679
- Example Script Processing 682
- Appendix A 685
- Assertions 685
- AXI4 Assertions 698
- Appendix B 715
- Programs 715
- Appendix C 751
- End-User License Agreement 779
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