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3–16 Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
ALTMEMPHY Signals
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation
Table 3–7. Local Interface Signals for DDR2 and DDR SDRAM—nonAFI (Part 1 of 2) (Note 1)
Signal Name Type Width Description
local_address input LOCAL_IF_
AWIDTH
The address corresponding to a write or read
request.
local_be input LOCAL_IF_
DWIDTH / 8
The input to ALTMEMPHY megafunction indicating
the byte-enable flags.
local_read_req input 1 The active-high signal requesting a read command
to the address on the ctl_address bus.
local_ready output 1 The controller-ready signal which indicates that the
currently asserted read or write request has been
accepted. The address of the request is sampled
when both the ready and request signals are high.
local_size input LOCAL_
BURST_LEN_
BITS
The controller signal to indicate the size (length) of
the burst transfer, fixed at 1 for this version.
local_wdata input LOCAL_IF_
DWIDTH
The write data from the user to the ALTMEMPHY
megafunction.
local_wdata_req output 1 The controller request for write data; not required
when the controller has an Avalon-MM interface.
local_write_req input 1 The active-high signal specifying that a write
command should be issued to the address on the
ctl_address signal.
local_refresh_req input 1 The ALTMEMPHY megafunction receives refresh
requests from the local interface and passes them to
the controller via ctl_refresh_req when in
user mode (ctl_usr_mode output is high).
local_burstbegin input 1 The ALTMEMPHY megafunction receives the
burstbegin signal from the local interface and
passes it to the controller via ctl_burstbegin
when in user mode (ctl_usr_mode output is
high).
local_rdata output LOCAL_IF_
DWIDTH
When ctl_usr_mode is high, this output passes
through the read data from the controller to the local
interface. Otherwise, it is tied low.
local_rdata_valid output 1 When ctl_usr_mode is high, this output passes
through the read data valid signal
(ctl_rdata_valid) from the controller to the
local interface. Otherwise, it is driven low.
local_init_done output 1 When ctl_usr_mode is high, this output passes
through the controller’s initialization done signal
(ctl_init_done) from the controller to the local
interface. Otherwise, it is driven low.
local_refresh_ack output 1 When ctl_usr_mode is high, this output passes
through the controller’s refresh acknowledge signal
(ctl_refresh_ack) from the controller to the
local interface. Otherwise, it is driven low.
local_autopch_req input 1 User control for auto precharge to request the
controller to issue an autoprecharge write or
autoprecharge read command.
- 1
- Contents 3
- 1. About this Megafunction 5
- 2. Parameter Settings 7
- Memory Settings 8
- QDR II+/QDR II SRAM 9
- Note to Table 2–3: 12
- Note to Table 2–5: 13
- Emulated Device 14
- Actual Device 14
- Figure 2–4. Preset Editor 15
- (nonAFI) 17
- PHY-to-Controller Interfaces 20
- Initialization Timing 21
- Note to Figure 3–5: 23
- ALTMEMPHY Signals 25
- Notes to Table 3–1: 26
- Note to Table 3–2: 27
- Notes to Table 3–5: 28
- Note to Table 3–6: 31
- Note to Table 3–7: 33
- Note to Table 3–8: 35
- QDR II+/QDR II SRAM Signals 36
- Note to Table 3–11: 37
- Note to Table 3–14: 39
- Note to Table 3–15: 39
- Understanding the Testbench 41
- Functional Memory Use 42
- Figure 3–6. Example Testbench 44
- Initialization Stage 45
- Write Training Data Stage 47
- Read Calibration Phase 49
- Functional Memory Use Stage 53
- Additional Debug Signals 55
- Calibration Status Interface 56
- Design Considerations 57
- Local Interface Requirements 58
- Notes to Figure 3–12: 59
- Notes to Figure 3–13: 61
- Notes to Figure 3–14: 64
- Notes to Figure 3–15: 66
- DDR2/DDR SDRAM 69
- Clock and Reset Management 71
- Stratix II GX devices use 73
- Notes to Table 4–1: 74
- Write Datapath 76
- Address and Command Datapath 77
- ), write_clk_2x (270), or 78
- Full-Rate Support 79
- Additional Information 81
- How to Contact Altera 82
- Typographic Conventions 82
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