Altera External Memory PHY Interface Manual de usuario descargar pdf (Pagina 23)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–7

Initialization Timing

DDR2 SDRAM Initialization Timing

The DDR2 SDRAM high-performance controller initializes the memory devices by

issuing the following command sequence:

■ NOP (for 200 µs, programmable)

■ PCH

■ ELMR, register 2

■ ELMR, register 3

■ ELMR, register 1

■ LMR

■ PCH

■ ARF

■ LMR

■ ELMR, register 1

Figure 3–5 shows a typical DDR2 SDRAM initialization timing sequence, which is

described below. The length of time between the reset and the clock enable signal

going high should be 200 µs. The value that you choose for the Memory initialization

time at power up (tINIt) setting in the MegaWizard interface is only used for

hardware that you generate. The controller simulation model is created with a much

shorter t

INIT

time to make simulation easier.

Figure 3–5. DDR2 SDRAM Device Initialization Timing

Note to Figure 3–5:

(1) local_init_done only goes high when calibration has completed.

Key:

P = PCH

L = LMR

A = ARF

clk

ddr_cke

ddr_a

ddr_ba

ddr_cs_n

ddr_ras_n

ddr_cas_n

ddr_we_n

local_init_done

DDR Command

2 0 3 0 1 0 0 1 0 1 11

0 0 0 0 0 0 0

P L L L L P A A L N L LL

200 clock cycles

[1] [2] [3] [3] [4] [7][6][5] [7] [8] [9]

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 82 83

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Altera External Memory PHY Interface Manual de usuario Pagina 23

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