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Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–9
ALTMEMPHY Signals
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
ALTMEMPHY Signals
This section describes the ALMEMPHY megafunction signals for the following
interfaces:
■ DDR2 and DDR SDRAM signals
■ QDR II+ and QDR II SRAM signals
DDR2 and DDR SDRAM Signals
Table 3–1 through Table 3–10 show the signals for DDR2 and DDR SDRAM nonAFIs.
The signal lists include the following signal groups:
■ I/O interface to the external memory device
■ Clock and reset signals
■ PLL reconfiguration signals
■ External DLL signals
■ User-mode calibrated on-chip termination (OCT) control signals
■ Interface to the memory controller
■ Local interface signals
■ Datapath interface for the controller
■ ALTMEMPHY megafunction calibration status interface
■ Additional calibration signals from the sequencer
1 Ports with the prefix “mem_” connect the PHY with the memory device; ports with the
prefix “ctl_” connect the PHY with the controller. Ports with prefix “ctl_mem_”
indicate the datapath for the controller; ports with the prefix “local_” indicate the
signal to be connected with the example driver or user logic.
1 Signals with suffix _n are active low; signals without suffix _n are active high.
Table 3–1. I/O Interface for DDR2 and DDR SDRAM—nonAFI (Note 1) (Part 1 of 2)
Signal Name Type Width Description
mem_addr output MEM_IF_ROWADDR_WIDTH The memory row and column address bus.
mem_ba output MEM_IF_BANKADDR_WIDTH The memory bank address bus.
mem_cas_n output 1 The memory column address strobe.
mem_cke output MEM_IF_CS_WIDTH The memory clock enable.
mem_clk bidir MEM_IF_CLK_PAIR_COUNT The memory clock, positive edge clock. (2)
mem_clk_n bidir MEM_IF_CLK_PAIR_COUNT The memory clock, negative edge clock. (2)
mem_cs_n output MEM_IF_CS_WIDTH The memory chip select signal.
mem_dm output MEM_IF_DM_WIDTH The optional memory data mask bus.
mem_dq bidir MEM_IF_DWIDTH The memory bidirectional data bus.
mem_dqs bidir MEM_IF_DWIDTH /
MEM_IF_DQ_PER_DQS
The memory bidirectional data strobe bus.
- 1
- Contents 3
- 1. About this Megafunction 5
- 2. Parameter Settings 7
- Memory Settings 8
- QDR II+/QDR II SRAM 9
- Note to Table 2–3: 12
- Note to Table 2–5: 13
- Emulated Device 14
- Actual Device 14
- Figure 2–4. Preset Editor 15
- (nonAFI) 17
- PHY-to-Controller Interfaces 20
- Initialization Timing 21
- Note to Figure 3–5: 23
- ALTMEMPHY Signals 25
- Notes to Table 3–1: 26
- Note to Table 3–2: 27
- Notes to Table 3–5: 28
- Note to Table 3–6: 31
- Note to Table 3–7: 33
- Note to Table 3–8: 35
- QDR II+/QDR II SRAM Signals 36
- Note to Table 3–11: 37
- Note to Table 3–14: 39
- Note to Table 3–15: 39
- Understanding the Testbench 41
- Functional Memory Use 42
- Figure 3–6. Example Testbench 44
- Initialization Stage 45
- Write Training Data Stage 47
- Read Calibration Phase 49
- Functional Memory Use Stage 53
- Additional Debug Signals 55
- Calibration Status Interface 56
- Design Considerations 57
- Local Interface Requirements 58
- Notes to Figure 3–12: 59
- Notes to Figure 3–13: 61
- Notes to Figure 3–14: 64
- Notes to Figure 3–15: 66
- DDR2/DDR SDRAM 69
- Clock and Reset Management 71
- Stratix II GX devices use 73
- Notes to Table 4–1: 74
- Write Datapath 76
- Address and Command Datapath 77
- ), write_clk_2x (270), or 78
- Full-Rate Support 79
- Additional Information 81
- How to Contact Altera 82
- Typographic Conventions 82
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1
Contents
9
Contents xi
11
Chapter 1
19
Overview
19
1-2 Overview
20
1-4 Overview
22
Chapter 2
23
Chapter 3
49
Utility and
49
• MS-DOS
65
• NetWare
65
Chapter 4
85
4.4.12 Exit
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Chapter 5
103
Start the
103
5.2.2 Features
105
Chapter 6
131
Virtual Sizing
131
Expansion
131
Appendix A
135
MegaRAID Service
135
IX-2 Index
144
Index IX-3
145
IX-4 Index
146
Index IX-5
147
IX-6 Index
148
Index IX-7
149
IX-8 Index
150
Index IX-9
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IX-10 Index
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