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Chapter 2: Parameter Settings 2–7

Creating an Emulated x36 QDR II+/QDR II SRAM ALTMEMPHY Variation

From software implementation point of view, creating a ×36 emulated QDR II+/QDR

II SRAM interface is exactly the same as implementing an interface with two ×18

QDR II+/QDR II SRAM devices. In the Memory Settings page of the ALTMEMPHY

MegaWizard interface, select a ×18 QDR II+/QDR II SRAM with the same timing

specifications as ×36 QDR II+/QDR II SRAM device (see Figure 2–3).

For more information about ×36 emulation for QDR II+/QDR II SRAM interfaces,

refer to the Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II

GX, Stratix III and Stratix IV Devices section in Volume 2: Device, Pin, and Board Layout

Guidelines of the External Memory Interface Handbook.

Table 2–4. QDR II+/QDR II SRAM Initialization Options

Parameter Name Range Units Description

Memory burst

length

4 beats Sets the memory burst length for the interface. As the

QDR II+/QDR II SRAM ALTMEMPHY megafunction only

supports half-rate designs, only a memory burst length of four

is supported, which equates to a local burst length of one.

Memory latency

setting

1.5 (QDR II

SRAM) or 2.5

(QDR II+ SRAM)

Cycles Sets the memory latency. Altera devices only support latency of

2.5 for QDR II+ SRAM and 1.5 for QDR II SRAM. QDR II+

SRAM with latency of 2.0 is not supported with Altera devices,

even though the ALTMEMPHY MegaWizard interface shows

this as an option.

Table 2–5. QDR II+/QDR II SRAM Timing Parameter Settings

Parameter Name Range Units Description

200–500 ps Address setup time to K clock rise.

200–500 ps Control setup time to K clock rise.

200–500 ps Address hold time to K clock rise.

200–500 ps Control hold time after K clock rise.

200–500 ps D setup time to K clock rise.

200–500 ps D hold time to K clock rise.

CQHQV

200–500 ps Echo clock high to data valid.

CQHQX

200–500 ps Echo clock high to data invalid.

CQHCQnH

(1) 0–2,000 ps Echo clock high to inverted echo clock high.

CQH

(1) 0–2,000 ps Echo clock high.

Note to Table 2–5:

(1) This parameter is available for QDR II+ SRAM interfaces only.

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 82 83

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Altera External Memory PHY Interface Manual de usuario Pagina 13

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