Altera Arria GX Development Board Manual de usuario descargar pdf (Pagina 8)

1–2 Reference Manual Altera Corporation

Arria GX Development Board October 2007

General Description

The Arria GX development board has the following main features:

■ Arria GX EP1AGX60 chip in a 780-pin flip-chip FineLine BGA

(FBGA) package

■ PCIe x4 interface

■ An Altera High Speed Mezzanine Card (HSMC)

■ 32-MByte x 16 DDR2 SDRAM operating at 233 MHz

■ Two user push-button switches (and one that is also used as a global

reset)

■ Eight user LEDs

■ One octal user DIP switch

■ Re-programmability with dedicated circuitry to perform the

following Arria GX configuration schemes: fast passive parallel

(FPP), passive serial (PS), and compressed FPP

Board Component Blocks

The board features the following component blocks:

■ 780-pin Altera Arria GX EP1AGX60 FPGA

● 60K logic elements (LEs)

● Eight transceiver channels

● 128 18 X 18 multiplier blocks

● Four phase locked loops (PLLs)

● 395 user I/Os

■ Transceiver interfaces

● x4 PCI Express edge connector

● One HSMC with four transceivers

■ FPGA configuration circuitry

● JTAG interface

● MAX

II CPLD and 16-bit page mode flash memory

■ Clocking circuitry

● The Arria GX development board uses three clock oscillators on

the transceivers and user logic to support all Arria GX device

protocols:

• 62.5 MHz

• 100.00 MHz

• 125.00 MHz

● PCI Express clock input

● SMA connector for external clock input and output

■ General user and configuration interfaces

● LEDs:

• Two LEDs indicating PCIe x1 or x4 mode

• One transmit and one receive (TX/RX) LED for the PCIe

transceiver interface

• One transmit and one receive (TX/RX) LED for the HSMC

transceiver interface

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