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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
88
VHDL Master BFM
Master BFM Configuration
April 2014
Master BFM Configuration
A master BFM supports the full range of signals defined for the AMBA AXI4-Stream Protocol
Specification. It has parameters that you use to configure the widths of the data and ID signals,
and transaction fields to configure timeout factors, setup and hold times, and so on.
You can change the data and ID signal widths from their default setting by assigning them new
values, usually performed in the top-level module of the test bench. These new values are then
passed into the master BFM using a parameter port list of the master BFM module.
Table 8-1 lists the parameter names for the data and ID signals and their default values.
A master BFM has configuration fields that you set by calling the set_config() procedure to
configure timeout factors, setup and hold times, etc. You get the value of a configuration field
by calling the get_config() procedure. Table 8-2 describes the full list of configuration fields.
Table 8-1. Master BFM Signal Width Parameters
Signal Width Parameter Description
AXI4_ID_WIDTH ID signal width in bits. This applies to the TID signal.
Refer to the AMBA AXI4-Stream Protocol Specification
for more details. Default: 18.
AXI4_USER_WIDTH User data signal width in bits. This applies to the TUSER
signal. Refer to the AMBA AXI4-Stream Protocol
Specification for more details. Default: 8.
AXI4_DEST_WIDTH Destination routing signal width in bits. This applies to
the TDEST signal. Refer to the AMBA AXI4-Stream
Protocol Specification for more details. Default: 18.
AXI4_DATA_WIDTH Data signal width in bits. This applies to the TDATA
signal. Refer to the AMBA AXI4-Stream Protocol
Specification for more details. Default: 1024.
Table 8-2. Master BFM Configuration
Configuration Field Description
Timing Variables
AXI4STREAM_CONFIG_SETUP_TIME The setup-time prior to the active
edge of ACLK, in units of
simulator time-steps for all
signals.
1
Default: 0.
AXI4STREAM_CONFIG_HOLD_TIME The hold-time after the active
edge of ACLK, in units of
simulator time-steps for all
signals.
1
Default: 0.
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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