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Getting Started with Qsys and the BFMs
Setting Up Simulation from the Windows GUI
Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
201
April 2014
Cadence IES Example Script Processing
The example-ius.sh script described below is contained in the installed Mentor VIP AE
directory location axi4stream/qsys-examples/ex1_back_to_back_sv.
The Mentor VIP AE BFMs for AXI4-Stream are compiled. The ncsim_setup.sh simulation
script is generated by Qsys, along with the simulation model files.
#!/bin/sh
# Usage: <command> [32|64]
# 32 bit mode is run unless 64 is passed in as the first argument.
MENTOR_VIP_AE=${MENTOR_VIP_AE:-$QUARTUS_ROOTDIR/../ip/ \
altera/mentor_vip_ae}
if [ "$1" == "64" ]
then
export QUESTA_MVC_GCC_LIB=$MENTOR_VIP_AE/common/ \
questa_mvc_core/linux_x86_64_gcc-4.4_ius
export INCA_64BIT=1
else
export QUESTA_MVC_GCC_LIB=$MENTOR_VIP_AE/common/ \
questa_mvc_core/linux_gcc-4.4_ius
fi
export LD_LIBRARY_PATH=$QUESTA_MVC_GCC_LIB:$LD_LIBRARY_PATH
cd simulation/cadence
# Run once, just to execute the 'mkdir' for the libraries.
source ncsim_setup.sh SKIP_DEV_COM=1 SKIP_COM=1 SKIP_ELAB=1 SKIP_SIM=1
# Compile VIP
ncvlog -sv \
"$MENTOR_VIP_AE/common/questa_mvc_svapi.svh" \
"$MENTOR_VIP_AE/axi4stream/bfm/mgc_common_axi4stream.sv" \
"$MENTOR_VIP_AE/axi4stream/bfm/mgc_axi4stream_monitor.sv" \
"$MENTOR_VIP_AE/axi4stream/bfm/mgc_axi4stream_inline_monitor.sv" \
"$MENTOR_VIP_AE/axi4stream/bfm/mgc_axi4stream_master.sv" \
"$MENTOR_VIP_AE/axi4stream/bfm/mgc_axi4stream_slave.sv"
The three example test programs are compiled:
# Compile the test program
ncvlog -sv ../../master_test_program.sv
ncvlog -sv ../../monitor_test_program.sv
ncvlog -sv ../../slave_test_program.sv
The example top-level file is compiled:
# Compile the top
ncvlog -sv ../../top.sv
Elaboration and simulation starts with the ncsim_setup.sh command. The Cadence IES
simulator requires the SystemVerilog library path -sv_lib to be passed to the simulator.
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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