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SystemVerilog Tutorials
Verifying a Master DUT
Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
73
April 2014
Advanced Slave Test Program API Definition
Note
You are not required to edit the following Advanced Slave Test Program API unless
further analysis of the protocol transfer is required.
The remaining section of this tutorial presents a walk-through of the Advanced Slave Test
Program API within the slave BFM test program. It consists of a single initial block() that
receives protocol transfers, inserting a delay in the assertion of the TREADY signal, as detailed
in the Basic Slave Test Program API Definition.
initial block()
Within an initial block, the slave test program defines a transaction variable trans of type
axi4stream_transaction to hold the Transaction Record of the transaction, as shown in
Example 6-6. The initial wait for the ARESETn signal to be deactivated, followed by a positive
ACLK edge, satisfies the protocol requirement detailed in Section 2.7.2 of the AXI4-Stream
Protocol Specification.
Example 6-6. Initialization
initial
begin
int i;
bit last;
axi4stream_transaction trans;
/*******************
** Initialisation **
*******************/
bfm.wait_on(AXI4STREAM_RESET_POSEDGE);
bfm.wait_on(AXI4STREAM_CLOCK_POSEDGE);
To receive protocol transfers, you must create a slave transaction. Within a forever loop, the
create_slave_transaction() function is used to create a slave transaction and assigned to the
transaction variable trans, as shown in Example 6-7.
An inner while loop iterates until the last transfer has been received. On each iteration, a delay is
inserted before the TREADY signal is set to 1 by calling the ready_delay() task if
m_insert_wait is set to 1. After any TREADY delay, the blocking get_transfer() task is called
and waits for a transfer to be received.
If further analysis of the received transfer is required, you need to edit the Advanced Slave API
to achieve this. You can obtain details of the Transaction Record for the received transfer by
using the get*() tasks within the SystemVerilog Slave BFM.
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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