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Signal Direction Width Description
avalon_st_tx_
empty[]
In 2 Use this signal to specify the number of empty bytes
(not used) in the cycle that contain the end of a
packet.
• 0x0: All bytes are valid.
• 0x1: The last byte is invalid.
• 0x2: The last two bytes are invalid.
• 0x3: The last three bytes are invalid.
Avalon-ST RX Data Interface Signals
Table 5-7: Avalon-ST RX Data Interface Signals
Signal Direction Width Description
avalon_st_rx_
startofpacket
Out 1 When asserted, indicates the beginning of the RX
data.
avalon_st_rx_
endofpacket
Out 1 When asserted, indicates the end of the RX data.
avalon_st_rx_valid Out 1 When asserted, indicates that the avalon_st_rx_
data[] signal and other signals on this interface are
valid.
avalon_st_rx_ready In 1 Assert this signal when the client is ready to accept
data.
avalon_st_rx_
error[]
Out 6 When set to 1, the respective bits indicate an error
type:
• Bit 0—PHY error.
• For 10 Gbps, the data on xgmii_rx_data
contains a control error character (FE).
• For 10 Mbps,100 Mbps,1 Gbps, gmii_rx_err
or mii_rx_err is asserted.
• Bit 1—CRC error. The computed CRC value
does not match the CRC received.
• Bit 2—Undersized frame. The RX frame length
is less than 64 bytes.
• Bit 3—Oversized frame.
• Bit 4—Payload length error.
• Bit 5—Overflow error. The user application is
not ready to receive more data while still
receiving incoming data from the MAC IP core.
avalon_st_rx_data[]
Out 32 RX data to the client.
5-6
Avalon-ST RX Data Interface Signals
UG-01144
2014.12.15
Altera Corporation
Interface Signals for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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