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Word
Offset
Register Name Description Access HW Reset
Value
0x00A6 rx_crccheck_control CRC checking on receive.
• Bit 0—always set this bit to 0.
• Bit 1—CRC checking enable.
0: Ignores the CRC field.
1: Checks the CRC field and reports the
status to avalon_st_rx_error[1] and
avalon_st_rxstatus_error.
• Bits 31:2—reserved.
Configure this register before you enable
the MAC IP core for operations.
RW
0x2
0x00A8 rx_custom_preamble_forward
(7)
• Bit 0—configures the forwarding of the
custom preamble to the client.
0: Removes the custom preamble from
the RX frame.
1: Retains and forwards the custom
preamble to the client.
• Bits 31:1—reserved.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x00AA rx_preamble_control
(7)
• Bit 0—preamble passthrough enable on
receive.
0: Disables preamble passthrough. The
MAC IP core checks for START and
SFD during packet decapsulation
process.
1: Enables preamble passthrough. The
MAC IP core checks only for START
during packet decapsulation process.
• Bits 31:1—reserved.
Configure this register before you enable
the MAC IP core for operations.
RW
0x0
(7)
This register is used only when you turn on the Enable preamble pass-through mode option. It is reserved
when not used.
4-14
RX Configuration and Status Registers
UG-01144
2014.12.15
Altera Corporation
Configuration Registers for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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