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Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
Use this table to map the legacy Ethernet 10-Gbps MAC registers to the LL Ethernet 10G MAC registers.
Table 4-2: Register Mapping
Register Names (10-Gbps Ethernet MAC)
Offset
(10-Gbps Ethernet MAC)
Offset
(LL Ethernet 10G MAC)
MAC TX Configuration Registers
TX Packet Control 1000 020
TX Transfer Status 1001 Not used.
TX Pad Insertion Control 1040 024
TX CRC Insertion Control 1080 026
TX Packet Underflow Count[31:0] 10C0 03E
TX Packet Underflow Count[35:32] 10C1 03F
TX Preamble Pass-Through Mode Control 1100 028
TX Unidirectional 1120 070
TX Pause Frame Control 1140 040
TX Pause Frame Quanta 1141 042
TX Pause Frame Enable 1142 044
TX PFC0 Pause Quanta 1180 048
TX PFC1 Pause Quanta 1181 049
TX PFC2 Pause Quanta 1182 04A
TX PFC3 Pause Quanta 1183 04B
TX PFC4 Pause Quanta 1184 04C
TX PFC5 Pause Quanta 1185 04D
TX PFC6 Pause Quanta 1186 04E
TX PFC7 Pause Quanta 1187 04F
TX PFC0 Hold-off Quanta 1190 058
TX PFC1 Hold-off Quanta 1191 059
TX PFC2 Hold-off Quanta 1192 05A
TX PFC3 Hold-off Quanta 1193 05B
TX PFC4 Hold-off Quanta 1194 05C
TX PFC5 Hold-off Quanta 1195 05D
TX PFC6 Hold-off Quanta 1196 05E
TX PFC7 Hold-off Quanta 1197 05F
TX PFC Enable 11A0 046
4-2
Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
UG-01144
2014.12.15
Altera Corporation
Configuration Registers for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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