Altera Cyclone V SoC Development Board Manual de usuario descargar pdf (Pagina 52)

2–44 Chapter 2: Board Components

Memory

Cyclone V SoC Development Board November 2013 Altera Corporation

Reference Manual

DDR3_HPS_ODT

H28 1.5-V SSTL Class I On-die termination enable

DDR3_HPS_RASN

D30 1.5-V SSTL Class I Row address select

DDR3_HPS_RESETN

P30 1.5-V SSTL Class I Reset

DDR3_HPS_WEN

C28 1.5-V SSTL Class I Write enable

DDR3_HPS_ZQ2

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U14)

DDR3_HPS_A0

F26 1.5-V SSTL Class I Address bus

DDR3_HPS_A1

G30 1.5-V SSTL Class I Address bus

DDR3_HPS_A2

F28 1.5-V SSTL Class I Address bus

DDR3_HPS_A3

F30 1.5-V SSTL Class I Address bus

DDR3_HPS_A4

J25 1.5-V SSTL Class I Address bus

DDR3_HPS_A5

J27 1.5-V SSTL Class I Address bus

DDR3_HPS_A6

F29 1.5-V SSTL Class I Address bus

DDR3_HPS_A7

E28 1.5-V SSTL Class I Address bus

DDR3_HPS_A8

H27 1.5-V SSTL Class I Address bus

DDR3_HPS_A9

G26 1.5-V SSTL Class I Address bus

DDR3_HPS_A10

D29 1.5-V SSTL Class I Address bus

DDR3_HPS_A11

C30 1.5-V SSTL Class I Address bus

DDR3_HPS_A12

B30 1.5-V SSTL Class I Address bus

DDR3_HPS_A13

C29 1.5-V SSTL Class I Address bus

DDR3_HPS_A14

H25 1.5-V SSTL Class I Address bus

DDR3_HPS_BA0

E29 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA1

J24 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA2

J23 1.5-V SSTL Class I Bank address bus

DDR3_HPS_CASN

E27 1.5-V SSTL Class I Row address select

DDR3_HPS_CKE

L29 1.5-V SSTL Class I Column address select

DDR3_HPS_CLK_P

L23 1.5-V SSTL Class I Differential output clock

DDR3_HPS_CLK_N

M23 1.5-V SSTL Class I Differential output clock

DDR3_HPS_CSN

H24 1.5-V SSTL Class I Chip select

DDR3_HPS_DM0

K28 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DM1

M28 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DQ0

K23 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ1

K22 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ2

H30 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ3

G28 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ4

L25 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ5

L24 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ6

J30 1.5-V SSTL Class I Data bus

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board

Reference

Schematic

Signal Name

Cyclone V SoC

Pin Number

I/O Standard Description

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 67 68

Comentarios a estos manuales

Sin comentarios

Altera Cyclone V SoC Development Board Manual de usuario Pagina 52

Comentarios a estos manuales

Relacionado con productos y manuales para Instrumentos de medición Altera Cyclone V SoC Development Board