Altera Cyclone V SoC Development Board Manual de usuario descargar pdf (Pagina 39)

Chapter 2: Board Components 2–31

Components and Interfaces

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

Figure 2–9 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as

various differential I/O standards including, but not limited to, LVDS, mini-LVDS,

and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to

either the generic single-ended pin-out or generic differential pin-out.

Table 2–23 lists the HSMC interface pin assignments, signal names, and functions.

Figure 2–9. HSMC Signal and Bank Diagram

Bank 3

Power

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2

Power

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1

4 TX Channels CDR

4 RX Channels CDR

JTAG

SMB

CLKIN0, CLKOUT0

Table 2–23. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference (J12)

Schematic Signal

Name

Cyclone V SoC

Pin Number

I/O Standard Description

HSMA_TX_P0

P4 1.5-V PCML Transmit channel

HSMA_RX_P0

R2 1.5-V PCML Receive channel

HSMA_TX_N0

P3 1.5-V PCML Transmit channel

HSMA_RX_N0

R1 1.5-V PCML Receive channel

HSMA_TX_P1

M4 1.5-V PCML Transmit channel

HSMA_RX_P1

N2 1.5-V PCML Receive channel

HSMA_TX_N1

M3 1.5-V PCML Transmit channel

HSMA_RX_N1

N1 1.5-V PCML Receive channel

HSMA_TX_P2

K4 1.5-V PCML Transmit channel

HSMA_RX_P2

L2 1.5-V PCML Receive channel

HSMA_TX_N2

K3 1.5-V PCML Transmit channel

HSMA_RX_N2

L1 1.5-V PCML Receive channel

HSMA_TX_P3

H4 1.5-V PCML Transmit channel

HSMA_RX_P3

J2 1.5-V PCML Receive channel

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 67 68

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