Altera Cyclone V SoC Development Board Manual de usuario descargar pdf (Pagina 35)

Chapter 2: Board Components 2–27

Components and Interfaces

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

Table 2–19 lists the Ethernet PHY interface pin assignments.

The Micrel KSZ9021RN PHY uses a multi-level POR bootstrap encoding scheme to

allow a small set of I/O pins (7) to set up a very large number of default settings

within the device. The related I/O pins have integrated pull-up or pull-down resistors

to configure the device. Table 2–20 lists the level encoding scheme.

Table 2–19. Ethernet PHY Pin Assignments, Signal Names and Functions

Board

Reference

(U11)

Schematic Signal Name

Cyclone V SoC

Pin Number

I/O Standard Description

CLK125_NDO_LED_MODE

— — Clock out 125-MHz LED mode

ENET_HPS_GTX_CLK

H19 3.3-V CMOS 125-MHz RGMII transmit clock

ENET_HPS_INTN

C19 3.3-V CMOS Management bus interrupt

ENET_HPS_LED1_LINK

— 3.3-V CMOS Receive data active LED

ENET_HPS_LED2_LINK

— 3.3-V CMOS Transmit data active LED

ENET_HPS_MDC

B21 3.3-V CMOS Management bus data clock

ENET_HPS_MDIO

E21 3.3-V CMOS Management bus data

ENET_HPS_RESETN

— 3.3-V CMOS Device reset

ENET_HPS_RSET

— 3.3-V CMOS Device interrupt

ENET_HPS_RX_CLK

G20 3.3-V CMOS RGMII receive clock

ENET_HPS_RX_DV

K17 3.3-V CMOS RGMII receive data valid

ENET_HPS_RXD0

A21 3.3-V CMOS RGMII receive data bus

ENET_HPS_RXD1

B20 3.3-V CMOS RGMII receive data bus

ENET_HPS_RXD2

B18 3.3-V CMOS RGMII receive data bus

ENET_HPS_RXD3

D21 3.3-V CMOS RGMII receive data bus

ENET_HPS_TX_EN

A20 3.3-V CMOS RGMII transmit enable

ENET_HPS_TXD0

F20 3.3-V CMOS RGMII transmit data bus

ENET_HPS_TXD1

J19 3.3-V CMOS RGMII transmit data bus

ENET_HPS_TXD2

F21 3.3-V CMOS RGMII transmit data bus

ENET_HPS_TXD3

F19 3.3-V CMOS RGMII transmit data bus

Table 2–20. Ethernet PHY (HPS) Bootstrap Encoding Scheme

Board Reference

(U11)

Schematic Signal Name Description Strapping Option

ENET_HPS_LED1_LINK

PHY address bit 0 Pulled low

ENET_HPS_LED2_LINK

PHY address bit 1 Pulled low

ENET_HPS_RXD0

Mode 0 Pulled high

ENET_HPS_RXD1

Mode 1 Pulled high

ENET_HPS_RXD2

Mode 2 Pulled high

ENET_HPS_RXD3

Mode 3 Pulled high

ENET_HPS_RX_CLK

PHY address bit 2 Pulled high

ENET_HPS_RX_DV

Clock enable Pulled low

CLK125_NDO_LED_MODE

Single LED mode Pulled high

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 67 68

Comentarios a estos manuales

Sin comentarios

Altera Cyclone V SoC Development Board Manual de usuario Pagina 35

Comentarios a estos manuales

Relacionado con productos y manuales para Instrumentos de medición Altera Cyclone V SoC Development Board