Altera ALTDQ_DQS2 Manual de usuario descargar pdf (Pagina 8)

Figure 6: IP Core Generated Files

Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

<your_ip>_sim

<Altera IP>_instance.vo - IPFS model

<simulator_vendor>

<your_ip>.qip - Quartus II IP integration file

<your_ip>.sip - Lists files for simulation

<your_ip>_testbench or _example - Testbench or example

<your_ip>.v, .sv. or .vhd - Top-level IP synthesis file

<AlteraIP_name>_instance

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist

<your_ip>.cmp - VHDL component declaration file

<your_ip>.bsf - Block symbol schematic file

<your_ip> - IP core synthesis files

<your_ip>.sv, .v, or .vhd - HDL synthesis files

<your_ip>.sdc - Timing constraints file

<your_ip>.ppf - XML I/O pin information file

<your_ip>.spd - Combines individual simulation scripts

<your_ip>_sim.f - Refers to simulation models and scripts

Upgrading IP Cores

IP core variants generated with a previous version of the Quartus II software may require upgrading

before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to

identify and upgrade IP core variants.

The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or

unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can

compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support

automatic upgrade.

The upgrade process renames and preserves the existing variation file (.v, .sv, or .vhd) as <my_variant>_

BAK.v, .sv, .vhd in the project directory.

Upgrading IP Cores

UG-01089

2014.12.17

Altera Corporation

ALTDQ_DQS2 IP Core User Guide

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