Altera ALTDQ_DQS2 Manual de usuario Pagina 61
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- Tabla de contenidos
- MARCADORES
- ALTDQ_DQS2 IP Core User Guide 1
- Related Information 2
- Using the Parameter Editor 4
- Adding IP Cores to IP Catalog 4
- Changes search path order 5
- Figure 5: IP Parameter Editor 7
- Upgrading IP Cores 8
- ALTDQ_DQS2 Parameter Settings 11
- Altera recommends using 12
- UG-01089 13
- 2014.12.17 13
- ALTDQ_DQS2 Data Paths 17
- Altera Corporation 18
- Send Feedback 18
- Block Name Description 19
- FIFO Control 21
- DQ and DQS Output Path 22
- ALTDQ_DQS2 Ports 24
- ALTDQ_DQS2 Data Strobe Ports 26
- ALTDQ_DQS2 Data Ports 29
- Port Name Type Width 30
- Description 30
- ALTDQ_DQS2 PLL and DLL Ports 33
- ALTDQ_DQS2 Hard FIFO Ports 34
- Ports Type Width Description 35
- Max Value Inc. Unit 50
- Stratix V Design Example 59
- Instantiating ALT_OCT IP Core 61
- Instantiating Altera PLL 62
- Clock Description 63
- Component Description 66
- Dynamic Configuration 67
- DQS Delay Chain 70
- Hard Read FIFO 71
- Implement as Soft FIFOs 72
- SDC Walkthrough 73
- Arria V Design Example 77
- VFIFO, LFIFO, and Read FIFO 89
- DQS Enable Control 91
- Analyzing Same Edge Transfer 93
- Timing Violation 95
- IP-Generate Command 96
- Document Revision History 97
- Date Version Changes 100
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