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ALTDQ_DQS2 PLL and DLL Ports

Table 9: ALTDQ_DQS2 PLL and DLL Ports

Port name Type Width Description

dll_delayctrl_in[]

Input 7 Receives the 7-bit delay settings

from the dll_delayctrlout port of

the ALTDLL instance. This 7-bit

signal controls delay through the

DQS delay chains. Compilation

error occurs if this port is not

connected to a DLL.

This port is supported in Arria V,

Cyclone V, and Stratix V devices.

fr_clock_in

Input 1 Receives the full-rate clock signal

from a clock pin, or the PLL clock

output port.

This port is supported in Arria V,

Cyclone V, and Stratix V devices.

hr_clock_in

Input 1 Receives the half-rate clock signal

from a clock pin, or the PLL clock

output port.

This port is supported in Arria V,

Cyclone V, and Stratix V devices.

Note: For more information about DLL in Stratix V device, refer to “Delay-Locked Loop” in the External

Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook.

Note: For more information about PLL in Stratix V devices, refer to “PLL Specifications” in DC and

Switching Characteristics for Stratix V Devices chapter of the Stratix V Device Handbook.

UG-01089

2014.12.17

ALTDQ_DQS2 PLL and DLL Ports

ALTDQ_DQS2 IP Core User Guide

Altera Corporation

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Altera ALTDQ_DQS2 Manual de usuario Pagina 33