Altera Stratix II GX EP2SGX90 Transceiver Signal Integrit Manual de usuario descargar pdf (Pagina 19)

Altera Corporation Reference Manual 2–9

May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board

Board Components & Interfaces

Figure 2–3 shows the clock signals passing through logic translators and

automatically routing to the appropriate destination.

Figure 2–3. Clocking Circuitry Automatic Routing Paths

Clock Buffer Functional Descriptions

This section provides functional descriptions for the board’s three clock

buffers:

■ ICS557-03 (U5)

■ ICS8543 (U8)

■ ICS83023 (U7)

ICS557-03

ICS83023

refclk1 in Quad1

refclk0 in Quad2

PCI-Express Trigger Clock (J3)

refclk1 in Quad2

refclk1 in Quad3

refclk0 in Quad1

refclk0 in Quad3

Global Clock for FPGA Block

General Purpose

Clocking Buffer:

2:1 Multiplexer

to a 1:4 LVDS

Fanout

Buffer (U8)

Spread Spectrum

Clock Generator for PCI-Express (U5)

ICS8543

50 MHz

Oscillator

Output Clock

from FPGA Side

(P = J11, N = J13)

SMA Connector Clock

Input (P = J5, N = J6)

Differential I/O to

LVCMOS Translator (U7)

SMA

Connector

Clock Input

(P= J12, N = J14)

156 MHz

Oscillator

25 MHz

Oscillator

= LVPECL/LVDS Input

= HCSL Output

= LVDS Output

Basic Trigger Clock (J4)

(P = J7, N = J8)

(P = J9, N = J10)

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 39 40

Comentarios a estos manuales

Sin comentarios

Altera Stratix II GX EP2SGX90 Transceiver Signal Integrit Manual de usuario Pagina 19

Comentarios a estos manuales

Relacionado con productos y manuales para Instrumentos de medición Altera Stratix II GX EP2SGX90 Transceiver Signal Integrit