Altera Stratix II GX EP2SGX90 Transceiver Signal Integrit Manual de usuario descargar pdf (Pagina 12)

2–2 Reference Manual Altera Corporation

Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006

Board Overview

Figure 2–1 shows the top view of the Stratix II GX EP2SGX90 transceiver

signal integrity development board.

Figure 2–1. Top View of the Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board

Clock

Setting

DIP Switch

Bank (S8)

User DIP Switch

Bank (S7)

User Push-Button

Switches (S1 through S6)

Stratix II GX Device (U20)

Dual 7-Segment

Displays (D9, D10)

Power Switch (S10)

User LEDs

(D1 through D8)

Slide

Switch (S9)

Debug

Header (J1)

Clock

Generator (U5)

Differential

Fan-out

Buffer (U8)

Differential to

Single-Ended

Buffer (U7)

156.25-MHz

Oscillator (U9)

25-MHz

Crystal (U6)

EPCS64 Device (U22)

16 Mbytes Flash

Memory (U19)

USB Connector (J2)

USB Interface (U2)

Temperature Sensor

with Alarm (U17)

SMA Transmit &

Receive Connectors

(J26 through J49)

Power Supply Input

10-pin Configuration Header

for EPCS64 Device (J23)

10-pin JTAG Configuration

Header for FPGA (J24)

Configuration

Done LED (D14)

Optional Power Input

Connection Jacks (J15, J17-21)

Jumper Header for

VCCH Voltage (J50)

SMA Input Clock

Connectors for FPGA (J12, J14)

SMA Output Clock Connectors

Reference Clock for Quad 1

Transceivers (J7, J8)

SMA Output Clock Connectors

Reference Clock for Quad 3

Transceivers (J9, J10)

50-MHz Oscillator

Used for System Clock (U10)

Power LED (D13)

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 39 40

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