Altera Quartus II Settings File Manual de usuario

Quartus Settings File Reference Manual2015.05.04MNL-Q21005SubscribeSend FeedbackAdvanced I/O Timing AssignmentsBOARD_MODEL_EBD_FAR_ENDSpecifies the fa

BOARD_MODEL_NEAR_DIFFERENTIAL_RSpecifies, in ohms, the board trace model near differential resistance.TypeStringDevice SupportThis setting can be used

HDL_MESSAGE_ONSpecifies the list of HDL message ids you want to turn on for this project.TypeIntegerDevice SupportThis setting can be used in projects

POWER_REPORT_POWER_DISSIPATIONSpecifies whether the PowerPlay Power Analyzer should report the thermal power dissipation calculatedduring power analys

POWER_REPORT_SIGNAL_ACTIVITYSpecifies whether the PowerPlay Power Analyzer should report the signal activities assumed for poweranalysis, and the sour

POWER_SIGNAL_ACTIVITY_END_TIMESpecifies the time at which toggle rates and static probabilities should stop being calculated for the outputsignals con

POWER_SIGNAL_ACTIVITY_START_TIMESpecifies the time at which toggle rates and static probabilities should start to be calculated for the outputsignals

POWER_STATIC_PROBABILITYSpecifies the fraction of time the signals generated by the node or entity are expected to be at VCC.Allowable values range fr

POWER_TJ_VALUESpecifies the junction temperature value, in degrees Celsius, used during power estimation.TypeIntegerDevice SupportThis setting can be

POWER_TOGGLE_RATESpecifies the toggle rate assumed by power estimation for the signals generated by this node or entity. Theunits for this value are t

POWER_TOGGLE_RATE_PERCENTAGESpecifies the toggle rate, as a percentage of clock domain frequency, assumed by power estimation for thesignals generated

POWER_USE_CUSTOM_COOLING_SOLUTIONSpecifies whether a custom cooling solution is used during power estimation. For a custom coolingsolution, you must s

POWER_USE_DEVICE_CHARACTERISTICSSpecifies the device characteristics to be used during power estimation. Estimates are based on averagepower consumed

HPS_PARTITIONSpecifies whether an entity or instance is a special-purpose partition that models the internals of the HardProcessor System (HPS).TypeBo

POWER_USE_INPUT_FILESpecifies whether or not Signal Activity Files or VCD files should be used to initialize the toggle rates andstatic probabilities

POWER_USE_INPUT_FILESSpecifies whether or not Signal Activity Files or VCD files should be used to initialize the toggle rates andstatic probabilities

POWER_USE_PVASpecifies whether or not Power Vectorless Activity should be used to fill in undefined toggle rates andstatic probabilities.TypeBooleanDe

POWER_USE_TA_VALUESpecifies the ambient temperature value, in degrees Celsius, used during power estimation.TypeIntegerDevice SupportThis setting can

POWER_VCCAUX_USER_OPTIONAllows you to specify settings for the VCCAUX power rail supply. Refer to the device datasheet for thecurrent device family fo

POWER_VCCA_GXBL_USER_OPTIONAllows you to specify settings for the VCCA_GXBL power rail supply. Refer to the device datasheet forthe current device fam

POWER_VCCA_GXBR_USER_OPTIONAllows you to specify settings for the VCCA_GXBR power rail supply. Refer to the device datasheet forthe current device fam

POWER_VCCA_GXB_USER_OPTIONAllows you to specify settings for the VCCA_GXB power rail supply. Refer to the device datasheet for thecurrent device famil

POWER_VCCA_L_USER_OPTIONAllows you to specify settings for the VCCA_L power rail supply. Refer to the device datasheet for thecurrent device family fo

POWER_VCCA_R_USER_OPTIONAllows you to specify settings for the VCCA_R power rail supply. Refer to the device datasheet for thecurrent device family fo

IGNORE_CARRY_BUFFERSIgnores CARRY_SUM buffers that are instantiated in the design. The Ignore CARRY Buffers option isignored if it is applied to anyth

POWER_VCCCB_USER_OPTIONAllows you to specify settings for the VCCCB power rail supply. Refer to the device datasheet for thecurrent device family for

POWER_VCCH_GXBL_USER_OPTIONAllows you to specify settings for the VCCH_GXBL power rail supply. Refer to the device datasheet forthe current device fam

POWER_VCCH_GXBR_USER_OPTIONAllows you to specify settings for the VCCH_GXBR power rail supply. Refer to the device datasheet forthe current device fam

POWER_VCCH_GXB_USER_OPTIONAllows you to specify settings for the VCCH_GXB power rail supply. Refer to the device datasheet for thecurrent device famil

POWER_VCCIO_USER_OPTIONAllows you to specify settings for the VCCIO power rail supply. Refer to the device datasheet for thecurrent device family for

POWER_VCCL_GXB_USER_OPTIONAllows you to specify settings for the VCCL_GXB power rail supply. Refer to the device datasheet for thecurrent device famil

POWER_VCCPD_USER_OPTIONAllows you to specify settings for the VCCPD power rail supply. Refer to the device datasheet for thecurrent device family for

POWER_VCCR_GXBL_USER_OPTIONAllows you to specify settings for the VCCR_GXBL power rail supply. Refer to the device datasheet for thecurrent device fam

POWER_VCCR_GXBR_USER_OPTIONAllows you to specify settings for the VCCR_GXBR power rail supply. Refer to the device datasheet forthe current device fam

POWER_VCCR_GXB_USER_OPTIONAllows you to specify settings for the VCCR_GXB power rail supply. Refer to the device datasheet for thecurrent device famil

IGNORE_CASCADE_BUFFERSIgnores CASCADE buffers that are instantiated in the design. This option is ignored if it is applied toanything other than an in

POWER_VCCT_GXBL_USER_OPTIONAllows you to specify settings for the VCCT_GXBL power rail supply. Refer to the device datasheet for thecurrent device fam

POWER_VCCT_GXBR_USER_OPTIONAllows you to specify settings for the VCCT_GXBR power rail supply. Refer to the device datasheet forthe current device fam

POWER_VCCT_GXB_USER_OPTIONAllows you to specify settings for the VCCT_GXB power rail supply. Refer to the device datasheet for thecurrent device famil

POWER_VCD_FILE_END_TIMESpecifies the time at which toggle rates and static probabilities should stop being calculated for the outputsignals contained

POWER_VCD_FILE_START_TIMESpecifies the time at which toggle rates and static probabilities should start to be calculated for the outputsignals contain

POWER_VCD_FILTER_GLITCHESSpecifies whether or not glitch filtering should be used when reading in VCD files.TypeBooleanDevice SupportThis setting can

VCCAUX_SHARED_USER_VOLTAGESpecifies the voltage of the VCCAUX_SHARED power rail supply. Refer to the device datasheet for thecurrent device family for

VCCAUX_USER_VOLTAGESpecifies the voltage of the VCCAUX power rail supply. Refer to the device datasheet for the currentdevice family for more details.

VCCA_FPLL_USER_VOLTAGESpecifies the voltage of the VCCA_FPLL power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCA_GTBR_USER_VOLTAGESpecifies the voltage of the VCCA_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

IGNORE_GLOBAL_BUFFERSIgnores GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied toanything other than an indi

VCCA_GTB_USER_VOLTAGESpecifies the voltage of the VCCA_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCA_GXBL_USER_VOLTAGESpecifies the voltage of the VCCA_GXBL power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCA_GXBR_USER_VOLTAGESpecifies the voltage of the VCCA_GXBR power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCA_GXB_USER_VOLTAGESpecifies the voltage of the VCCA_GXB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCA_L_USER_VOLTAGESpecifies the default voltage of the VCCA_L power rail supply, which is applied if all transceivers on theleft side of the device a

VCCA_PLL_USER_VOLTAGESpecifies the voltage of the VCCA_PLL power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCA_R_USER_VOLTAGESpecifies the default voltage of the VCCA_R power rail supply, which is applied if all transceivers on theright side of the device

VCCA_USER_VOLTAGESpecifies the voltage of the VCCA power rail supply. For devices in the Arria II family, this voltage isapplied if the transceivers a

VCCBAT_USER_VOLTAGESpecifies the voltage of the VCCBAT power rail supply. Refer to the device datasheet for the currentdevice family for more details.

VCCCB_USER_VOLTAGESpecifies the voltage of the VCCCB power rail supply. Refer to the device datasheet for the current devicefamily for more details.Ty

IGNORE_LCELL_BUFFERSIgnores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anythingother than an indivi

VCCD_FPLL_USER_VOLTAGESpecifies the voltage of the VCCD_FPLL power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCD_PLL_USER_VOLTAGESpecifies the voltage of the VCCD_PLL power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCD_USER_VOLTAGESpecifies the voltage of the VCCD power rail supply. Refer to the device datasheet for the current devicefamily for more details.Type

VCCEH_GXBL_USER_VOLTAGESpecifies the default voltage of the VCCEH_GXBL power rail supplies, which is applied if all transceiversin the corresponding t

VCCEH_GXBR_USER_VOLTAGESpecifies the default voltage of the VCCEH_GXBR power rail supplies, which is applied if all transceiversin the corresponding t

VCCEH_GXB_USER_VOLTAGESpecifies the default voltage of the VCCEH_GXB power rail supplies, which is applied if all transceivers inthe corresponding tra

VCCE_GXBL_USER_VOLTAGESpecifies the default voltage of the VCCE_GXBL power rail supplies, which is applied if all transceivers inthe corresponding tra

VCCE_GXBR_USER_VOLTAGESpecifies the default voltage of the VCCE_GXBR power rail supplies, which is applied if all transceivers inthe corresponding tra

VCCE_GXB_USER_VOLTAGESpecifies the default voltage of the VCCE_GXB power rail supplies, which is applied if all transceivers inthe corresponding trans

VCCE_USER_VOLTAGESpecifies the voltage of the VCCE power rail supply. Refer to the device datasheet for the current devicefamily for more details.Type

IGNORE_MAX_FANOUT_ASSIGNMENTSDirects the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity, or the wholedesign. For HCII migrati

VCCHIP_L_USER_VOLTAGESpecifies the voltage of the VCCHIP_L power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCHIP_R_USER_VOLTAGESpecifies the voltage of the VCCHIP_R power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCHIP_USER_VOLTAGESpecifies the voltage of the VCCHIP power rail supply. Refer to the device datasheet for the current devicefamily for more details.

VCCHSSI_L_USER_VOLTAGESpecifies the voltage of the VCCHSSI_L power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCHSSI_R_USER_VOLTAGESpecifies the voltage of the VCCHSSI_R power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCH_GTBR_USER_VOLTAGESpecifies the voltage of the VCCH_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

VCCH_GTB_USER_VOLTAGESpecifies the voltage of the VCCH_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCH_GXBL_USER_VOLTAGESpecifies the default voltage of the VCCH_GXBL power rail supplies, which is applied if all transceivers inthe corresponding tra

VCCH_GXBR_USER_VOLTAGESpecifies the default voltage of the VCCH_GXBR power rail supplies, which is applied if all transceivers inthe corresponding tra

VCCH_GXB_USER_VOLTAGESpecifies the voltage of the VCCH_GXB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

IGNORE_ROW_GLOBAL_BUFFERSIgnores ROW GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied toanything other than

VCCH_L_USER_VOLTAGESpecifies the default voltage of the VCCH_L power rail supplies, which is applied if all transceivers in thecorresponding transceiv

VCCH_R_USER_VOLTAGESpecifies the default voltage of the VCCH_R power rail supplies, which is applied if all transceivers in thecorresponding transceiv

VCCINT_USER_VOLTAGESpecifies the voltage of the VCCINT power rail supply. Refer to the device datasheet for the current devicefamily for more details.

VCCIO_USER_VOLTAGESpecifies the voltage of the VCCIO power rail supply. Refer to the device datasheet for the current devicefamily for more details.Ty

VCCL_GTBL_USER_VOLTAGESpecifies the voltage of the VCCL_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

VCCL_GTBR_USER_VOLTAGESpecifies the voltage of the VCCL_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

VCCL_GTB_USER_VOLTAGESpecifies the voltage of the VCCL_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCL_GXBL_USER_VOLTAGESpecifies the voltage of the VCCL_GXBL power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCL_GXBR_USER_VOLTAGESpecifies the voltage of the VCCL_GXBR power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCL_GXB_USER_VOLTAGESpecifies the voltage of the VCCL_GXB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

IGNORE_SOFT_BUFFERSIgnores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anythingother than an individu

VCCL_USER_VOLTAGESpecifies the voltage of the VCCL power rail supply. Refer to the device datasheet for the current devicefamily for more details.Type

VCCPD_USER_VOLTAGESpecifies the voltage of the VCCPD power rail supply. Refer to the device datasheet for the current devicefamily for more details.Ty

VCCPGM_USER_VOLTAGESpecifies the voltage of the VCCPGM power rail supply. Refer to the device datasheet for the currentdevice family for more details.

VCCPLL_HPS_USER_VOLTAGESpecifies the voltage of the VCC_PLL_HPS power rail supply. For more information, refer to therespective device datasheet.TypeS

VCCPT_USER_VOLTAGESpecifies the voltage of the VCCPT power rail supply. Refer to the device datasheet for the current devicefamily for more details.Ty

VCCP_USER_VOLTAGESpecifies the voltage of the VCCP power rail supply. Refer to the device datasheet for the current devicefamily for more details.Type

VCCRSTCLK_HPS_USER_VOLTAGESpecifies the voltage of the VCCRSTCLK_HPS power rail supply. Refer to the device datasheet for thecurrent device family for

VCCR_GTBL_USER_VOLTAGESpecifies the voltage of the VCCR_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

VCCR_GTBR_USER_VOLTAGESpecifies the voltage of the VCCR_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

VCCR_GTB_USER_VOLTAGESpecifies the voltage of the VCCR_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFFInstructs Analysis & Synthesis to ignore all translate_off/synthesis_off synthesis directives in your Verilo

VCCR_GXBL_USER_VOLTAGESpecifies the voltage of the VCCR_GXBL power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCR_GXBR_USER_VOLTAGESpecifies the voltage of the VCCR_GXBR power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCR_GXB_USER_VOLTAGESpecifies the voltage of the VCCR_GXB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCR_L_USER_VOLTAGESpecifies the voltage of the VCCR_L power rail supply. Refer to the device datasheet for the current devicefamily for more details.

VCCR_R_USER_VOLTAGESpecifies the voltage of the VCCR_R power rail supply. Refer to the device datasheet for the current devicefamily for more details.

VCCR_USER_VOLTAGESpecifies the voltage of the VCCR power rail supply. Refer to the device datasheet for the current devicefamily for more details.Type

VCCT_GTBL_USER_VOLTAGESpecifies the voltage of the VCCT_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

VCCT_GTBR_USER_VOLTAGESpecifies the voltage of the VCCT_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more det

VCCT_GTB_USER_VOLTAGESpecifies the voltage of the VCCT_GTB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCT_GXBL_USER_VOLTAGESpecifies the voltage of the VCCT_GXBL power rail supply. Refer to the device datasheet for the currentdevice family for more de

BOARD_MODEL_NEAR_PULLDOWN_RSpecifies, in ohms, the board trace model near pull-down resistance.TypeStringDevice SupportThis setting can be used in pro

IGNORE_VERILOG_INITIAL_CONSTRUCTSInstructs Analysis & Synthesis to ignore initial constructs and variable declaration assignments in yourVerilog H

VCCT_GXBR_USER_VOLTAGESpecifies the voltage of the VCCT_GXBR power rail supply. Refer to the device datasheet for the currentdevice family for more de

VCCT_GXB_USER_VOLTAGESpecifies the voltage of the VCCT_GXB power rail supply. Refer to the device datasheet for the currentdevice family for more deta

VCCT_L_USER_VOLTAGESpecifies the voltage of the VCCT_L power rail supply. Refer to the device datasheet for the current devicefamily for more details.

VCCT_R_USER_VOLTAGESpecifies the voltage of the VCCT_R power rail supply. Refer to the device datasheet for the current devicefamily for more details.

VCCT_USER_VOLTAGESpecifies the voltage of the VCCT power rail supply. Refer to the device datasheet for the current devicefamily for more details.Type

VCC_HPS_USER_VOLTAGESpecifies the voltage of the VCC_HPS power rail supply. For more information, refer to the respectivedevice datasheet.TypeStringDe

VCC_USER_VOLTAGESpecifies the voltage of the VCC power rail supply. Refer to the device datasheet for the current devicefamily for more details.TypeSt

Programmer AssignmentsGENERATE_CONFIG_HEXOUT_FILEGenerates a Hexadecimal (Intel-format) Output File (.hexout) containing configuration data that can b

GENERATE_CONFIG_ISC_FILEGenerates an In System Configuration File (.isc) containing configuration data that an intelligent externalcontroller can use

GENERATE_CONFIG_JAM_FILEGenerate a JEDEC STAPL Format File (.jam) containing configuration data that an intelligent externalcontroller can use to conf

IMPLEMENT_AS_CLOCK_ENABLESpecifies that this node should function as a clock enable signal for one or more registers.TypeBooleanDevice SupportThis set

GENERATE_CONFIG_JBC_FILEGenerate a compressed Jam STAPL Byte Code 2.0 File (.jbc) containing configuration data that anintelligent external controller

GENERATE_CONFIG_JBC_FILE_COMPRESSEDGenerate a compressed Jam STAPL Byte Code 2.0 File (.jbc) containing configuration data that anintelligent external

GENERATE_CONFIG_SVF_FILEGenerates a Serial Vector Format File (.svf) containing configuration data that an intelligent externalcontroller can use to c

GENERATE_ISC_FILEDirects the programmer to generate an In System Configuration File (.isc) containing configuration datathat an intelligent external c

GENERATE_JAM_FILEDirects the programmer to generate a JEDEC JESD71 STAPL Format File (.jam) containing configurationdata that an intelligent external

GENERATE_JBC_FILEDirects the programmer to generate a compressed JAM Byte Code File (.jbc) containing configurationdata that an intelligent external c

GENERATE_JBC_FILE_COMPRESSEDGenerate a compressed JAM Byte Code File (.jbc) containing configuration data that an intelligentexternal controller can u

GENERATE_SVF_FILEDirects the programmer to generate a Serial Vector Format File (.svf) containing configuration data thatan intelligent external contr

HPS_EARLY_IO_RELEASERelease the HPS shared I/O bank after the IOCSR programmingTypeBooleanDevice SupportThis setting can be used in projects targeting

ISP_CLAMP_STATESpecifies the pin state during in-system programming. This option is ignored if it is assigned to anythingother than pins.TypeEnumerati

IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELLImplements the output of a primitive in a logic cell. You can apply this option to a logic function thatwould not ord

ISP_CLAMP_STATE_DEFAULTFor used pins that do not have an in-system programming clamp state assignment, this option allows youto specify the state that

MERGE_HEX_FILEUses the Hexadecimal (Intel-Format) File (.hex) and the programmable logic Partial SRAM Object File(.psof) to create passive programming

Project-Wide AssignmentsAGGREGATE_REVISIONSpecifies an AGGREGATE revision type.TypeStringDevice SupportThis setting can be used in projects targeting

AHDL_FILEAssociates an AHDL source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

AHDL_TEXT_DESIGN_OUTPUT_FILEAssociates an AHDL Text Design Output File with this project.TypeFile nameDevice SupportThis setting can be used in projec

ASM_FILEAssociates an Assembly source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera devi

AUTO_EXPORT_VER_COMPATIBLE_DBAutomatically exports version-compatible database files when compilation completes.TypeBooleanDevice SupportThis setting

BASE_REVISIONSpecifies a BASE revision type.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe v

BASE_REVISION_PROJECT_OUTPUT_DIRECTORYSpecifies the directory where project output files such as the Text-Format Report Files (.rpt) and EquationFiles

BDF_FILEAssociates a Block Design File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device f

INFER_RAMS_FROM_RAW_LOGICInstructs the Compiler to infer RAM from registers and multiplexers. Some HDL patterns that differ fromAltera RAM templates a

BINARY_FILEAssociates a binary file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device fami

BSF_FILEAssociates a Block Symbol File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device f

CDF_FILEAssociates a Chain Description File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera dev

COMMAND_MACRO_FILEAssociates a script file or ModelSim Macro File with this project.TypeFile nameDevice SupportThis setting can be used in projects ta

CPP_FILEAssociates a C++ source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device fam

CPP_INCLUDE_FILEAssociates a C++ include file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera d

CUSP_FILEAssociates a C++ source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device fa

CVP_REVISIONSpecifies a CVP revision type.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe val

C_FILEAssociates a C source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.

DEPENDENCY_FILEAssociates a Dependency file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera dev

IP_SEARCH_PATHSSpecifies the IP search paths specific to the project.TypeStringDevice SupportThis setting can be used in projects targeting any Altera

DSPBUILDER_FILEAssociates a DSPBuilder source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Alt

EDIF_FILEAssociates an EDIF source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

ELF_FILEAssociates an ELF file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.No

ENABLE_COMPACT_REPORT_TABLEAllows you to view the report table in compact format.TypeBooleanDevice SupportThis setting can be used in projects targeti

ENABLE_REDUCED_MEMORY_MODEDetermines whether to enable compiler to run in reduced memory mode. This assignment controls asmall number of memory-intens

EQUATION_FILEAssociates an Equation File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

FLOW_DISABLE_ASSEMBLERAllows you to turn on or turn off the Assembler during compilation.TypeBooleanDevice SupportThis setting can be used in projects

FLOW_ENABLE_HC_COMPAREEnable HardCopy Compare during compilationTypeBooleanDevice SupportThis setting can be used in projects targeting any Altera dev

FLOW_ENABLE_IO_ASSIGNMENT_ANALYSISAllows you to run I/O assignment analysis before compilationTypeBooleanDevice SupportThis setting can be used in pro

FLOW_ENABLE_PARALLEL_MODULESAllows you to run Assembler and TimeQuest Timing Analyzer in parallel during compilation.TypeBooleanDevice SupportThis set

LCELL_INSERTIONAllows you to insert one or more logic cells between two nodes without changing the design files. Thevalue you assign this option is th

FLOW_ENABLE_POWER_ANALYZERAllows you to turn on or turn off the Power Analyzer during compilation.TypeBooleanDevice SupportThis setting can be used in

FLOW_ENABLE_RTL_VIEWERAllows the RTL Viewer to process the schematic during design compilation. Turning on this option alsoallows you to open the RTL

FLOW_HARDCOPY_DESIGN_READINESS_CHECKAllows you to turn on or turn off the HardCopy Design Readiness Check during compilation.TypeBooleanDevice Support

GDF_FILEAssociates a GDF source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device fam

HC_OUTPUT_DIRSpecifies the directory to which HardCopy handoff files should be generatedTypeFile nameDevice SupportThis setting can be used in project

HEX_FILEAssociates a Hexadecimal source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera de

HEX_OUTPUT_FILEAssociates a Hexadecimal Output File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Al

HPS_ISW_FILEAssociates a hard processor system (HPS) initial software configuration file with an HPS entity.TypeFile nameDevice SupportThis setting ca

HTML_FILEAssociates an HTML file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.

HTML_REPORT_FILEAssociates an HTML Report File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera

LIMIT_AHDL_INTEGERS_TO_32_BITSSpecifies whether an AHDL-based design should have a limit on integer size of 32 bits. This option isprovided for backwa

INCLUDE_FILEAssociates an Include File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device f

IPA_FILEAssociates an IP Advisor file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device fa

IPX_FILEAssociates a Quartus II IP-XACT description file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting a

IP_COMPONENT_AUTHORSpecifies the IP component authorTypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.No

IP_COMPONENT_DESCRIPTIONSpecifies the IP component descriptionTypeStringDevice SupportThis setting can be used in projects targeting any Altera device

IP_COMPONENT_DISPLAY_NAMESpecifies the IP component display nameTypeStringDevice SupportThis setting can be used in projects targeting any Altera devi

IP_COMPONENT_DOCUMENTATION_LINKSpecifies a documentation link for the IP componentTypeStringDevice SupportThis setting can be used in projects targeti

IP_COMPONENT_GROUPSpecifies the group in the Component Library that includes this IP componentTypeStringDevice SupportThis setting can be used in proj

IP_COMPONENT_INTERNALSpecifies the if the IP is an internal component.TypeBooleanDevice SupportThis setting can be used in projects targeting any Alte

IP_COMPONENT_NAMESpecifies the IP component nameTypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesT

MAX7000_FANIN_PER_CELLSpecifies the maximum fan-in per macrocell. Legal integer values, in percentage terms, range from 20through 100.Old NameMaximum

IP_COMPONENT_PARAMETERSpecifies the parameter, value, and display name of an IP component parameterTypeStringDevice SupportThis setting can be used in

IP_COMPONENT_REPORT_HIERARCHYSpecifies the if the IP component should report its hierarchyTypeBooleanDevice SupportThis setting can be used in project

IP_COMPONENT_VERSIONSpecifies the IP component versionTypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.

IP_GENERATED_DEVICE_FAMILYSpecifies the device families for which the IP core was generated for.TypeStringDevice SupportThis setting can be used in pr

IP_QSYS_MODEMode used to generate a QIPTypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe value

IP_TARGETED_DEVICE_FAMILYSpecifies the device family for which the IP core was targeted.TypeStringDevice SupportThis setting can be used in projects t

IP_TARGETED_PART_TRAITSpecifies a part traint for which IP core was targeted.TypeStringDevice SupportThis setting can be used in projects targeting an

IP_TOOL_ENVSpecifies the tool which generated the IP core.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device fam

IP_TOOL_HIERARCHY_LEVELSSpecifies the number of levels of hierarchy from the IP root.TypeIntegerDevice SupportThis setting can be used in projects tar

IP_TOOL_NAMESpecifies the IP core name.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe value

MAX7000_IGNORE_LCELL_BUFFERSIgnores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anythingother than a

IP_TOOL_VERSIONSpecifies the IP core versionTypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe v

ISC_FILEIEEE 1532 fileTypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe value of this assign

JAM_FILEAssociates a Jam File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.Not

JBC_FILEAssociates a Jam Byte-Code File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

LICENSE_FILEAssociates a License File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device fa

LMF_FILEAssociates a Library Mapping File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera devic

LOGIC_ANALYZER_INTERFACE_FILEAssociates a Logic Analyzer Interface file with this project.TypeFile nameDevice SupportThis setting can be used in proje

MAP_FILEEPC16 addresses usedTypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe value of this

MASK_REVISIONSpecifies a MASK revision type.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe v

MESSAGE_DISABLETells the compiler to suppress the specified user message(s).TypeIntegerDevice SupportThis setting can be used in projects targeting an

MAX7000_IGNORE_SOFT_BUFFERSIgnores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anythingother than an

MESSAGE_ENABLETells the compiler to enable the specified user message(s).TypeIntegerDevice SupportThis setting can be used in projects targeting any A

MIF_FILEAssociates a Memory Initialization File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera

MIGRATION_DIFFERENT_SOURCE_FILESpecifies a HDL source file that will be different in the companion revision. This is used to allow settingdifferences

MISC_FILEAssociates a file with this project. Files assigned to this assignment will be archived by the Project Archivecommand if the 'Project so

NUM_PARALLEL_PROCESSORSSpecifies the maximum number of processors allocated for parallel compilation on a single machine. Forparallel compilation you

OBJECT_FILEAssociates an Object file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device fam

OCP_FILESpecifies the OpenCore core plus file generated by the MegaWizard. This file is used by Quartus to allowcompilation and sof generation of the

PARTIAL_SRAM_OBJECT_FILEAssociates a Partial SRAM Object File with this project.TypeFile nameDevice SupportThis setting can be used in projects target

PDC_FILEAssociates a Physical Design Constraint File (.pdc) with this project.TypeFile nameDevice SupportThis setting can be used in projects targetin

PERSONA_FILEAssociates a Quartus II Persona with this project as a source file.TypeFile nameDevice SupportThis setting can be used in projects targeti

BOARD_MODEL_NEAR_PULLUP_RSpecifies, in ohms, the board trace model near pull-up resistance.TypeStringDevice SupportThis setting can be used in project

MAX7000_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance orminimize logic u

PIN_FILEAssociates a Pin-Out File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family

POWER_INPUT_FILEAssociates a Power Input File (.pwf) with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any A

PPF_FILESpecifies the name of the MegaWizard generated .ppf file containing core specific pin assignments. Thisfile will be loaded by Pin Planner.Type

PROGRAMMER_OBJECT_FILEAssociates a Programmer Object File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting

PROJECT_OUTPUT_DIRECTORYSpecifies the directory in which to save all project output files such as the Text-Format Report Files (.rpt)and Equation File

PROJECT_SHOW_ENTITY_NAMEDetermines whether to display the entity name for node namesTypeBooleanDevice SupportThis setting can be used in projects targ

PROJECT_USE_SIMPLIFIED_NAMESDetermines whether to use the simplified naming scheme.TypeBooleanDevice SupportThis setting can be used in projects targe

QARLOG_FILEAssociates an Archive Log file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera devic

QAR_FILEAssociates an Archive file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device famil

QIP_FILEAssociates a Quartus II IP file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of Compiler-synthesized parallel expander productterms.Old Nam

QSYS_FILEAssociates a Qsys file (.qsys) with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

QUARTUS_PTF_FILEAssociates a Peripheral Template File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any

QUARTUS_SBD_FILEAssociates a Quartus II System Build Descriptor File with this project.TypeFile nameDevice SupportThis setting can be used in projects

QUARTUS_STANDARD_DELAY_FILEAssociates a Quartus II Standard Delay Format File with this project.TypeFile nameDevice SupportThis setting can be used in

QVAR_FILEAssociates a Quartus II IP variation file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Alt

QXP_FILEAssociates a Quartus II Exported Partition (QXP) with this project as a source fileTypeFile nameDevice SupportThis setting can be used in proj

RAW_BINARY_FILEAssociates a Raw Binary File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera dev

READ_OR_WRITE_IN_BYTE_ADDRESSDetermines whether to read or write Hexadecimal(.hex) File in byte addressable mode for this project.TypeEnumerationValue

RECONFIGURABLE_REVISIONSpecifies a RECONFIGURABLE revision type.TypeStringDevice SupportThis setting can be used in projects targeting any Altera devi

REVISION_TYPEDescribes the type of revision. The possible revision types are BASE, RECONFIGURABLE,AGGREGATE, CVP, and MASK. The default type is BASE.T

MAXII_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,minimize logic usage

RUN_FULL_COMPILE_ON_DEVICE_CHANGERun Full Compilation when the device changesTypeBooleanDevice SupportThis setting can be used in projects targeting a

SAVE_MIGRATION_INFO_DURING_COMPILATIONOption to save out migration information during compilationOld NameHARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILA

SBI_FILEAssociates a Slave Binary Image File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera de

SDC_FILEAssociates a Synopsys Design Constraint File (.sdc) with this project.TypeFile nameDevice SupportThis setting can be used in projects targetin

SDF_OUTPUT_FILEAssociates a Standard Delay Format Output File with this project.TypeFile nameDevice SupportThis setting can be used in projects target

SERIAL_BITSTREAM_FILEAssociates a Serial Bitstream File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting an

SIGNALTAP_FILEAssociates a SignalTap II file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera de

SIP_FILEAssociates a Simulation IP File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

SLD_FILEAssociates a file with this project. Files assigned to this assignment will be archived by the Project Archivecommand if the 'Project sou

SMF_FILEAssociates a State Machine file (.smf) with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera

MAX_AUTO_GLOBAL_REGISTER_CONTROLSAllows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excludingclock signa

SOFTWARE_LIBRARY_FILEAssociates a Software library file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting an

SOPCINFO_FILEAssociates a Qsys or SOPC Builder report file with this project. If you select the Project source andsettings files option, the Project A

SOPC_FILEAssociates a SOPC Builder file (.sopc) with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera

SOURCE_TCL_SCRIPT_FILERuns Tcl script file. This assignment has the same effect as 'source <filename>'.TypeFile nameDevice SupportThis

SPD_FILEAssociates a Simulation Package Descriptor File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting an

SRAM_OBJECT_FILEAssociates an SRAM Object File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera

SRECORDS_FILEAssociates a Motorola S-Record file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Alter

SVF_FILEAssociates a Serial Vector Format File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera

SYM_FILEAssociates a Symbol File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.

SYNTHESIS_ONLY_QIPDetermines whether a Quartus II IP File is not for simulation.TypeBooleanDevice SupportThis setting can be used in projects targetin

MAX_BALANCING_DSP_BLOCKSAllows you to specify the maximum number of DSP blocks that the DSP block balancer will assume existin the current device for

SYSTEMVERILOG_FILEAssociates a SystemVerilog HDL source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeti

TCL_SCRIPT_FILEAssociates a Tcl script file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera dev

TEMPLATE_FILEAssociates a Template File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device

TEXT_FILEAssociates a text file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device family.N

TEXT_FORMAT_REPORT_FILEAssociates a text-format Report File with this project.TypeFile nameDevice SupportThis setting can be used in projects targetin

TIMING_ANALYSIS_OUTPUT_FILEAssociates a Timing Analysis Output File with this project.TypeFile nameDevice SupportThis setting can be used in projects

VCD_FILEAssociates a Verilog Value Change Dump File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Al

VECTOR_TABLE_OUTPUT_FILEAssociates a Vector Table Output File with this project.TypeFile nameDevice SupportThis setting can be used in projects target

VECTOR_TEXT_FILEAssociates a text-format Vector File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any A

VECTOR_WAVEFORM_FILEAssociates a Vector Waveform File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any

MAX_FANOUTDirects the Compiler to control the number of destinations the specified node feeds so the fan-out countdoes not exceed the value specified

VERILOG_FILEAssociates a Verilog HDL source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Alter

VERILOG_INCLUDE_FILEAssociates a Verilog Include file with this project.Old NameVERILOG_VH_FILETypeFile nameDevice SupportThis setting can be used in

VERILOG_OUTPUT_FILEAssociates a Verilog Output File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Al

VERILOG_TEST_BENCH_FILEAssociates a Verilog HDL Test Bench File (.vt) with this project.TypeFile nameDevice SupportThis setting can be used in project

VER_COMPATIBLE_DB_DIRSpecifies the directory to which version-compatible database files should be savedTypeFile nameDevice SupportThis setting can be

VHDL_FILEAssociates a VHDL source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera device f

VHDL_OUTPUT_FILEAssociates a VHDL Output File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any Altera d

VHDL_TEST_BENCH_FILEAssociates a VHDL Test Bench File (.vht) with this project.TypeFile nameDevice SupportThis setting can be used in projects targeti

VQM_FILEAssociates a structural Verilog HDL source file with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting an

ZIP_VECTOR_WAVEFORM_FILEAssociates a Compressed Vector Waveform File with this project.TypeFile nameDevice SupportThis setting can be used in projects

MAX_LABSAllows you to specify the maximum number of LABs that Analysis & Synthesis should try to utilize for adevice. This option overrides the us

SignalProbe AssignmentsSIGNALPROBE_ALLOW_OVERUSEThis option controls whether the Quartus II Fitter will move nodes in a design in order to ensure that

SIGNALPROBE_CLOCKRegisters the output of the SignalProbe node and assigns the specified clock to this register.TypeStringDevice SupportThis setting ca

SIGNALPROBE_DURING_NORMAL_COMPILATIONWhen enabled, SignalProbe signals will be routed during normal compilation.TypeBooleanDevice SupportThis setting

SIGNALPROBE_ENABLESelects whether SignalProbe routing is enabled for current node.TypeBooleanDevice SupportThis setting can be used in projects target

SIGNALPROBE_NUM_REGISTERSSpecifies the number of registers to insert before the output of the SignalProbe pin.TypeIntegerDevice SupportThis setting ca

SIGNALPROBE_SOURCEAssigns the source of the signal to be routed to the specified SignalProbe node.TypeStringDevice SupportThis setting can be used in

SignalTap II AssignmentsENABLE_LOGIC_ANALYZER_INTERFACEEnables Logic Analyzer Interface for compilationTypeBooleanDevice SupportThis setting can be us

ENABLE_SIGNALTAPEnables the SignalTap II Logic Analyzer for compilationTypeBooleanDevice SupportThis setting can be used in projects targeting any Alt

STP_FILEAssociates a SignalTap II Logic Analyzer File with this project.TypeFile nameDevice SupportThis setting can be used in projects targeting any

USE_LOGIC_ANALYZER_INTERFACE_FILESpecifies the Logic Analyzer Interface File to be used for compilation.TypeFile nameDevice SupportThis setting can be

MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMSAllows you to specify the maximum number of registers that Analysis & Synthesis can use for conversion

USE_SIGNALTAP_FILESpecifies the SignalTap II Logic Analyzer File to be used for compilation.TypeFile nameDevice SupportThis setting can be used in pro

Simulator AssignmentsACTIONSpecifies the breakpoint's action when triggered.TypeEnumerationValues• Give Error• Give Info• Give Warning• StopDevic

ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMSAdds output pins to the simulation vector output waveforms automatically.TypeBooleanDevice SupportThis

ADD_TO_SIMULATION_OUTPUT_WAVEFORMSAdds the signal to the list of signals for which output waveforms are shown in the simulation report. Thisoption mak

ALIASSpecifies an alias for the full hierarchical name of the node.TypeStringDevice SupportThis setting can be used in projects targeting any Altera d

AUTO_USE_SIMULATION_PDB_NETLISTAutomatically saves/loads simulation netlist to/from external fileTypeBooleanDevice SupportThis setting can be used in

BREAKPOINT_STATESpecifies the state of a breakpoint as either enabled or disabled.TypeEnumerationValues• Disabled• EnabledDevice SupportThis setting c

CHECK_OUTPUTSChecks expected outputs vs. actual outputs in the simulation report.TypeBooleanDevice SupportThis setting can be used in projects targeti

END_TIMESpecifies the end time for simulation.TypeTimeDevice SupportThis setting can be used in projects targeting any Altera device family.NotesNoneS

EXTERNAL_PIN_CONNECTIONSpecifies an external pin connection between an output pin and an input pin. This option is used duringsimulations only.TypeStr

MAX_RAM_BLOCKS_M4KAllows you to specify the maximum number of M4K,M9K,M20K,or M10K memory blocks that theCompiler may use for a device. This option ov

GLITCH_DETECTIONMonitors the design for user-defined glitches (spikes).TypeBooleanDevice SupportThis setting can be used in projects targeting any Alt

GLITCH_INTERVALAllows you to detect glitches and specify the time interval that defines a glitch. If two logic leveltransitions occur in a period shor

IMMEDIATE_ASSERTION_FAIL_ACTIONSpecifies the immediate assertion's action when the assertion fails.TypeEnumerationValues• Give Error• Give Info•

IMMEDIATE_ASSERTION_FAIL_MESSAGESpecifies the immediate assertion's message when the assertion fails.TypeStringDevice SupportThis setting can be

IMMEDIATE_ASSERTION_PASS_MESSAGESpecifies the immediate assertion's message when the assertion passes.TypeStringDevice SupportThis setting can be

IMMEDIATE_ASSERTION_STATESpecifies the state of an immediate assertion as either enabled or disabled.TypeEnumerationValues• Disabled• EnabledDevice Su

IMMEDIATE_ASSERTION_TEST_CONDITIONSpecifies the immediate assertion's test condition.TypeStringDevice SupportThis setting can be used in projects

INCREMENTAL_VECTOR_INPUT_SOURCESpecifies the source of input vectors to be used for simulation.TypeFile nameDevice SupportThis setting can be used in

PASSIVE_RESISTORSpecifies whether an output or bidirectional pin has a pull-up or pull-down resistor. This option is used infunctional simulations onl

SETUP_HOLD_DETECTIONDetects setup and hold time violations.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device f

MAX_RAM_BLOCKS_M512Allows you to specify the maximum number of M512 memory blocks that the Compiler may utilize for adevice. This option overrides the

SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLEDDisables setup and hold time violations detection in input registers of bi-directional pins.Ty

SETUP_HOLD_TIME_VIOLATION_DETECTIONEnables setup and hold time violation detection during simulation.TypeBooleanDevice SupportThis setting can be used

SIMULATION_BUS_CHANNEL_GROUPINGAutomatically groups bus channels in the output waveforms which are shown in the simulation report.TypeBooleanDevice Su

SIMULATION_CELL_DELAY_MODEL_TYPESpecifies the type of delay model to be used for cell delays : transport or inertialTypeEnumerationValues• Inertial• T

SIMULATION_COMPARE_SIGNALSpecifies the signal to be compared in a waveform comparison.TypeBooleanDevice SupportThis setting can be used in projects ta

SIMULATION_COMPLETE_COVERAGE_REPORT_PANELDisplay report on output ports that toggle between 1 and 0 during simulation.TypeBooleanDevice SupportThis se

SIMULATION_COVERAGEReports 'coverage,' that is, the ratio of output ports that toggle between 1 and 0 during simulation,compared to the tota

SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCESpecifies the default comparison timing tolerance to be used in a waveform comparison.TypeTimeDevice Suppor

SIMULATION_INTERCONNECT_DELAY_MODEL_TYPESpecifies the type of delay model to be used for interconnect delays : transport or inertialTypeEnumerationVal

SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANELDisplay report on output ports that do not toggle to 0 during simulation.TypeBooleanDevice SupportThis

BOARD_MODEL_NEAR_SERIES_RSpecifies, in ohms, the board trace model near series resistance.TypeStringDevice SupportThis setting can be used in projects

MAX_RAM_BLOCKS_MRAMAllows you to specify the maximum number of M-RAM/M144K memory blocks that the Compiler mayutilize for a device. This option overri

SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANELDisplay report on output ports that do not toggle to 1 during simulation.TypeBooleanDevice SupportThis

SIMULATION_MODESpecifies the type of simulation to perform for the current Simulation focus.TypeEnumerationValues• Functional• Timing• Timing using Fa

SIMULATION_NETLIST_VIEWEREnables the Simulation Netlist Viewer.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera devi

SIMULATION_SIGNAL_COMPARE_TOLERANCESpecifies the comparison timing tolerance to be used for each signal in a waveform comparison.TypeTimeDevice Suppor

SIMULATION_VDB_RESULT_FLUSHFlushes signal transitions from memory to disk for memory optimizationTypeBooleanDevice SupportThis setting can be used in

SIMULATION_VECTOR_COMPARE_BEGIN_TIMESpecifies the begin time at which waveform comparison on simulation results should start.TypeTimeDevice SupportThi

SIMULATION_VECTOR_COMPARE_END_TIMESpecifies the end time at which waveform comparison on simulation results should stop.TypeTimeDevice SupportThis set

SIMULATION_VECTOR_COMPARE_RULE_FOR_0Specifies vector values that match with expected strong low value (0) in the waveform fileTypeStringDevice Support

SIMULATION_VECTOR_COMPARE_RULE_FOR_1Specifies vector values that match with expected strong high value (1) in the waveform fileTypeStringDevice Suppor

SIMULATION_VECTOR_COMPARE_RULE_FOR_DCSpecifies vector values that match with expected don't care value (DC) in the waveform fileTypeStringDevice

MERCURY_CARRY_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of both user-entered and Compiler-synthesizedCARRY_SUM buffers. Carry chai

SIMULATION_VECTOR_COMPARE_RULE_FOR_HSpecifies vector values that match with expected weak high value (H) in the waveform fileTypeStringDevice SupportT

SIMULATION_VECTOR_COMPARE_RULE_FOR_LSpecifies vector values that match with expected weak low value (L) in the waveform fileTypeStringDevice SupportTh

SIMULATION_VECTOR_COMPARE_RULE_FOR_USpecifies vector values that match with expected uninitialized value (U) in the waveform fileTypeStringDevice Supp

SIMULATION_VECTOR_COMPARE_RULE_FOR_WSpecifies vector values that match with expected weak unknown value (W) in the waveform fileTypeStringDevice Suppo

SIMULATION_VECTOR_COMPARE_RULE_FOR_XSpecifies vector values that match with expected unknown value (X) in the waveform fileTypeStringDevice SupportThi

SIMULATION_VECTOR_COMPARE_RULE_FOR_ZSpecifies vector values that match with expected high impedance value (Z) in the waveform fileTypeStringDevice Sup

SIMULATION_WITH_AUTO_GLITCH_FILTERINGSpecifies whether or not glitch filtering should be performed during Timing Simulation.TypeEnumerationValues• Alw

SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOWSpecifies whether or not glitch filtering should be used when Generate Signal Activity File and Generat

SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAFSpecifies whether or not glitch filtering should be used when generating the Signal Activity File

SIMULATOR_GENERATE_POWERPLAY_VCD_FILESpecifies whether or not a VCD File for PowerPlay Power Analyzer should be written out.TypeBooleanDevice SupportT

MERCURY_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance orminimize logic u

SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILESpecifies whether or not a Signal Activity File should be written out.TypeBooleanDevice SupportThis setting can

SIMULATOR_POWERPLAY_VCD_FILE_END_TIMESpecifies the end time for the PowerPlay Power Analyzer VCD file.TypeTimeDevice SupportThis setting can be used i

SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATIONSpecifies the name the VCD File for PowerPlay Power Analyzer should be written to.TypeFile nameDevice S

SIMULATOR_POWERPLAY_VCD_FILE_START_TIMESpecifies the start time for the PowerPlay Power Analyzer VCD file.TypeTimeDevice SupportThis setting can be us

SIMULATOR_PVT_TIMING_MODEL_TYPESpecifies the type of PVT Timing Model to use for the current Simulation focus.TypeEnumerationValues• Auto• Model_1• Mo

SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIMESpecifies the time at which toggle rates and static probabilities should stop being calculated.TypeTimeDevice S

SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATIONSpecifies the name the Signal Activity File should be written to.TypeFile nameDevice SupportThis sett

SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIMESpecifies the time at which toggle rates and static probabilities should start to be calculated.TypeTimeDevic

SIM_BEHAVIOR_SIMULATIONPerform QUASAR Behavior simulation to simulate a verilog designTypeBooleanDevice SupportThis setting can be used in projects ta

SIM_COMPILE_HDL_FILESCollect a list of HDL files for compilation in QUASARTypeStringDevice SupportThis setting can be used in projects targeting any A

MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CAREAllows you to specify whether you want the TimeQuest Timing Analyzer to

SIM_HDL_TOP_MODULE_NAMETop level module name provided from user to determine starting point of simulationTypeStringDevice SupportThis setting can be u

SIM_OVERWRITE_WAVEFORM_INPUTSOverwrite simulation input file with simulation results.TypeBooleanDevice SupportThis setting can be used in projects tar

SIM_TAP_REGISTER_D_Q_PORTSAdds the D and Q ports of a register node to the list of signals for which output waveforms are shown inthe simulation repor

SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLESpecifies the duty cycle of compared clock used to trigger waveform comparison.TypeIntegerDevice SupportThis setti

SIM_VECTOR_COMPARED_CLOCK_OFFSETSpecifies the offset of compared clock used to trigger waveform comparison.TypeTimeDevice SupportThis setting can be u

SIM_VECTOR_COMPARED_CLOCK_PERIODSpecifies the period of compared clock used to trigger waveform comparison.TypeTimeDevice SupportThis setting can be u

START_TIMESpecifies the start time for simulation.TypeTimeDevice SupportThis setting can be used in projects targeting any Altera device family.Syntax

TRIGGER_EQUATIONSpecifies the breakpoint's trigger equation.TypeStringDevice SupportThis setting can be used in projects targeting any Altera dev

TRIGGER_VECTOR_COMPARE_ON_SIGNALTrigger vector comparison with the specified signal.TypeBooleanDevice SupportThis setting can be used in projects targ

USER_MESSAGESpecifies the breakpoint's message when triggered.TypeStringDevice SupportThis setting can be used in projects targeting any Altera d

MUX_RESTRUCTUREAllows the Compiler to reduce the number of logic elements required to implement multiplexers in adesign. This option is useful if your

VECTOR_COMPARE_TRIGGER_MODESpecifies the comparison mode to trigger vector comparison.TypeEnumerationValues• ALL_EDGE• INPUT_EDGE• SELECTED_EDGEDevice

VECTOR_INPUT_SOURCESpecifies the source of input vectors to be used for simulation.TypeFile nameDevice SupportThis setting can be used in projects tar

VECTOR_OUTPUT_DESTINATIONSpecifies the output vector file for the current simulation.TypeFile nameDevice SupportThis setting can be used in projects t

VECTOR_OUTPUT_FORMATSpecifies the format of simulation results.TypeEnumerationValues• CVWF• VCD• VWFDevice SupportThis setting can be used in projects

X_ON_VIOLATION_OPTIONGives user the option to see 'X' or valid data at the output of registers in the event of a timing violationduring simu

NOT_GATE_PUSH_BACKAllows the Compiler to push an inversion (that is, a NOT gate) back through a register and implement iton that register's data

NUMBER_OF_INVERTED_REGISTERS_REPORTEDAllows you to specify the maximum number of inverted registers that the Synthesis Report should display.TypeInteg

NUMBER_OF_REMOVED_REGISTERS_REPORTEDAllows you to specify the maximum number of removed registers that the Synthesis Report shoulddisplay.TypeIntegerD

NUMBER_OF_SWEPT_NODES_REPORTEDAllows you to specify the maximum number of swept nodes that the Synthesis Report displays. A sweptnode is any node whic

NUMBER_OF_SYNTHESIS_MIGRATION_ROWSAllows you to specify the maximum number of rows that a report in Synthesis Migration Checks shoulddisplay.TypeInteg

BOARD_MODEL_NEAR_TLINE_C_PER_LENGTHSpecifies, in farads/inch, the board trace model near transmission line distributed capacitance.TypeStringDevice Su

OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,minimize logic usage, or b

OPTIMIZE_POWER_DURING_SYNTHESISControls the power-driven compilation setting of Analysis & Synthesis. This option determines howaggressively Analy

PARALLEL_EXPANDER_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of Compiler-synthesized parallel expander productterms.Old NameParalle

PARALLEL_SYNTHESISOption to enable/disable parallel synthesisTypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device

PARAMETERAssigns an attribute that determines the logic created or used to implement the function, for example, thewidth of a bus. Parameters are char

POWER_UP_LEVELCauses a register to power up with the specified logic level, either High (1) or Low (0). If this option isspecified for an input pin, i

PRESERVE_FANOUT_FREE_NODEPrevents a register that has no fan-out from being removed during synthesis.TypeBooleanDevice SupportThis setting can be used

PRESERVE_REGISTERPrevents a register from minimizing away during synthesis and prevents sequential netlist optimizations.Sequential netlist optimizati

PRE_MAPPING_RESYNTHESISSpecifies that the Quartus II software should perform a resynthesis optimization step immediately beforetechnology mapping. The

PRPOF_IDSpecifies whether a register is a unique partial reconfiguration bitstream identifier. The same identifiervalue will be used to generate the p

BOARD_MODEL_NEAR_TLINE_LENGTHSpecifies, in inches, the board trace model near transmission line length.TypeStringDevice SupportThis setting can be use

RBCGEN_CRITICAL_WARNING_TO_ERRORTo convert Quartus II critical warning to error.TypeBooleanDevice SupportThis setting can be used in projects targetin

REMOVE_DUPLICATE_REGISTERSRemoves a register if it is identical to another register. If two registers generate the same logic, the secondone will be d

REMOVE_REDUNDANT_LOGIC_CELLSRemoves redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes acircuit for area and speed. Th

REPORT_CONNECTIVITY_CHECKSSpecifies whether the synthesis report should include the panels in the Connectivity Checks folderTypeBooleanDevice SupportT

REPORT_PARAMETER_SETTINGSSpecifies whether the synthesis report should include the panels in the Parameter Settings by EntityInstance folderOld NameSH

REPORT_SOURCE_ASSIGNMENTSSpecifies whether the synthesis report should include the panels in the Source Assignments folderTypeBooleanDevice SupportThi

RESYNTHESIS_OPTIMIZATION_EFFORTSpecifies whether the resynthesis tool should focus on fmax or area during resynthesis.TypeEnumerationValues• Low• Norm

RESYNTHESIS_PHYSICAL_SYNTHESISSpecifies the physical synthesis level for resynthesis.TypeEnumerationValues• ADVANCED• NormalDevice SupportThis setting

RESYNTHESIS_RETIMINGSpecifies the paths on which retiming will be performed: all paths, register-to-register paths only, or none.TypeEnumerationValues

SAFE_STATE_MACHINETells the compiler to implement state machines that can recover gracefully from an illegal state.TypeBooleanDevice SupportThis setti

BOARD_MODEL_NEAR_TLINE_L_PER_LENGTHSpecifies, in henrys/inch, the board trace model near transmission line distributed inductance.TypeStringDevice Sup

SAVE_DISK_SPACESaves disk space by reducing the number of node names available for entering assignments, simulation,timing analysis, reporting, etc.Ty

SEARCH_PATHSpecifies the path name of a user-defined library.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device

SHIFT_REGISTER_RECOGNITION_ACLR_SIGNALAllows the Compiler to find a group of shift registers of the same length that can be replaced with thealtshift_

SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGESAllows the Compiler to skip the fitting stage during smart recompilation when design changes may affe

STATE_MACHINE_PROCESSINGSpecifies the processing style used to compile a state machine. You can use your own 'User-Encoded' style,or select

STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECTDirects the compiler to not modify the Force Signal Detect and Signal Thresho

STRATIXII_CARRY_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of both user-entered and Compiler-synthesizedCARRY_SUM buffers. Carry ch

STRATIXII_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,minimize logic u

STRATIX_CARRY_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of both user-entered and Compiler-synthesizedCARRY_SUM buffers. Carry chai

STRATIX_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,minimize logic usa

BOARD_MODEL_TERMINATION_VSpecifies, in volts, the board trace model termination voltage.TypeStringDevice SupportThis setting can be used in projects t

STRICT_RAM_RECOGNITIONWhen this option is ON, the Compiler is only allowed to replace RAM if the hardware matches the designexactly.TypeBooleanDevice

SYNCHRONIZATION_REGISTER_CHAIN_LENGTHThis setting specifies the maximum number of registers in a row to be considered as a synchronizationchain. Synch

SYNTHESIS_EFFORTControls the synthesis trade-off between compilation speed and performance and area. The default is'Auto'. You can select &a

SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPERWhen this option is set to On, synthesis will keep the synchronous clear/preset behavior when re

SYNTHESIS_S10_MIGRATION_CHECKSOption to enable/disable Arria 10 to Stratix 10 Synthesis Migration Checks.TypeBooleanDevice SupportThis setting can be

SYNTH_CLOCK_MUX_PROTECTIONCauses the multiplexers in the clock network to be decomposed to 2to1 multiplexer trees, and protectedfrom being merged with

SYNTH_GATED_CLOCK_CONVERSIONAutomatically converts gated clocks in the design to use clock enable pins if clock enable pins are not usedin the origina

SYNTH_MESSAGE_LEVELSpecifies the type of Analysis & Synthesis messages you want to view. Setting this option to 'Low' allowsyou to view

SYNTH_PROTECT_SDC_CONSTRAINTCauses SDC constraint checking in register merging. It helps to maintain the validity of SDC constraintsthrough compilatio

SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAMSpecifies whether RAM, ROM, and shift-register inference should take the design and device resourcesinto a

BOARD_MODEL_TLINE_C_PER_LENGTHSpecifies, in farads/inch, the board trace model far transmission line distributed capacitance.TypeStringDevice SupportT

SYNTH_TIMING_DRIVEN_SYNTHESISAllows synthesis to use timing information during synthesis to better optimize the design.TypeBooleanDevice SupportThis s

TOP_LEVEL_ENTITYSpecifies the full hierarchichal path of the entity that is the focus of the current compilation or simulation.Old NameFOCUS_ENTITY_NA

TRUE_WYSIWYG_FLOWSpecifies that the Quartus II software should not try to optimize this WYSIWYG design.TypeBooleanDevice SupportThis setting can be us

USER_LIBRARIESSpecifies the pathnames of user-defined libraries.TypeStringDevice SupportThis setting can be used in projects targeting any Altera devi

USE_GENERATED_PHYSICAL_CONSTRAINTSSpecifies the physical constraints file generated by the resynthesis tool to be used by the Quartus IIsoftwareTypeBo

USE_HIGH_SPEED_ADDERTells the Compiler whether to use high speed adder circuitry to implement arithmetic functions or not.This option is useful for im

USE_LOGICLOCK_CONSTRAINTS_IN_BALANCINGDirects the compiler to use LogicLock constraints during DSP and RAM balancing.TypeBooleanDevice SupportThis set

VERILOG_CONSTANT_LOOP_LIMITDefines the iteration limit for Verilog loops with loop conditions that evaluate to compile-time constantson each loop iter

VERILOG_INPUT_VERSIONSpecifies the language dialect to use when processing Verilog Design Files: Verilog-1995 (IEEE Std.1364-1995), Verilog-2001 (IEEE

VERILOG_LMF_FILESpecifies the default Library Mapping File (.lmf) for the current compilation.TypeFile nameDevice SupportThis setting can be used in p

BOARD_MODEL_TLINE_LENGTHSpecifies, in inches, the board trace model far transmission line length.TypeStringDevice SupportThis setting can be used in p

VERILOG_MACRODefines Verilog HDL macro - same as `define directiveTypeStringDevice SupportThis setting can be used in projects targeting any Altera de

VERILOG_NON_CONSTANT_LOOP_LIMITDefines the iteration limit for Verilog loops with loop conditions that do not evaluate to compile-timeconstants on eac

VERILOG_SHOW_LMF_MAPPING_MESSAGESDetermines whether to display messages describing the mappings used in the Library Mapping File.TypeBooleanDevice Sup

VHDL_INPUT_LIBRARYSpecifies the logical name of a user-defined VHDL design library : physical name.TypeStringDevice SupportThis setting can be used in

VHDL_INPUT_VERSIONSpecifies the language dialect to use when processing VHDL Design Files: VHDL-1987 (IEEE Std1076-1987), VHDL-1993 (IEEE Std 1076-199

VHDL_LMF_FILESpecifies the default Library Mapping File (.lmf) for the current compilation.TypeFile nameDevice SupportThis setting can be used in proj

VHDL_SHOW_LMF_MAPPING_MESSAGESDetermines whether to display messages describing the mappings used in the Library Mapping File.TypeBooleanDevice Suppor

Assembler AssignmentsAPEX20K_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target APEXde

APEX20K_CONFIG_DEVICE_JTAG_USER_CODESpecifies user-defined information about the configuration device. The JTAG user code is an extension ofthe option

APEX20K_JTAG_USER_CODESpecifies user-defined information about the target device. The JTAG user code is an extension of theoption register. This data

BOARD_MODEL_EBD_FILE_NAMESpecifies the Electronic Board Description (EBD) file that contains the path description for an I/O pin.TypeStringDevice Supp

BOARD_MODEL_TLINE_L_PER_LENGTHSpecifies, in henrys/inch, the board trace model far transmission line distributed inductance.TypeStringDevice SupportTh

ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDEAllows signaldetect to propogate from PCS to the core, which will be blocked if you fix the CDR lockupissue. This

AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODEAutomatically increments the JTAG user code in the second and subsequent configuration devices if thetarget

AUTO_RESTART_CONFIGURATIONDirects the device to restart the configuration process automatically if a data error is encountered. If thisoption is turne

CLOCK_SOURCESpecifies whether the configuration device generates an internal clock or applies an external clock.TypeEnumerationValues• External• Inter

COMPRESSION_MODEAllows you to compress SRAM Object Files (.sof) stored in a Programmer Object File (.pof) for aconfiguration device.TypeBooleanDevice

CONFIGURATION_CLOCK_DIVISORSpecifies the clock frequency divisor, which is used to determine the period of the system clock.TypeStringDevice SupportTh

CONFIGURATION_CLOCK_FREQUENCYSpecifies the clock frequency of the configuration device.TypeStringDevice SupportThis setting can be used in projects ta

CYCLONEIII_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target device.TypeStringDevice

CYCLONEII_M4K_COMPATIBILITYDirect Quartus II software to produce programming files that are compatible with both rev A and rev Bsilicon. This option a

CYCLONE_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target Cyclonedevice.TypeStringDev

ENABLE_ADVANCED_IO_TIMINGAllows the TimeQuest Timing Analyzer to use Advanced I/O Timing to generate I/O timing results.Timing results are based on th

DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICEDisables the nCS and OE internal pull-ups on the configuration device(s).Old NameDISABLE_CONF_DONE_AND_NSTA

ENABLE_ADV_SEU_DETECTIONAllows you to enable the Advanced SEU Detection compiler to generate design SEU sensitivity map file. Ifthis option is turned

ENABLE_AUTONOMOUS_PCIE_HIPDirects the device to release the PCIe HIP after the periphery is configured and before core configurationis completed. This

ENABLE_IO_WEAK_PULL_UP_DURING_CONFIGSet the IO to weak pull-up during configuration. By default the IO will be set to input tri-statedOld NameAuto res

ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICEAllows an EPC1 configuration device to operate in a 3.3 V environment.TypeBooleanDevice SupportThis setting ca

ENABLE_OCT_DONEThis option controls whether the INIT_DONE signal will be gated by OCT_DONE signal which indicatesthe Power-Up OCT calibration is compl

EN_SPI_IO_WEEK_PULLUPSet SPI IO pins to week pull-up prior to usermode, otherwise SPI IO pins will be input tri-statedTypeBooleanDevice SupportThis se

EN_USER_IO_WEEK_PULLUPSet IO to week pull-up prior to usermode, otherwise IO will be input tri-statedTypeBooleanDevice SupportThis setting can be used

EPROM_USE_CHECKSUM_AS_USERCODEUses the checksum value from the Programmer Object File (.pof) as the JTAG user code.TypeBooleanDevice SupportThis setti

FLEX10K_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target FLEX10KE/10K/10KA/ACEX 1K d

OUTPUT_IO_TIMING_ENDPOINTSpecifies the node at which output I/O Timing ends.TypeEnumerationValues• Far End• Near EndDevice SupportThis setting can be

FLEX10K_CONFIG_DEVICE_JTAG_USER_CODESpecifies user-defined information about the configuration device. The JTAG user code is an extension ofthe option

FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICEAllows an EPC1 configuration device to operate in a 3.3-V environment.TypeBooleanDevice SupportThis se

FLEX10K_JTAG_USER_CODESpecifies user-defined information about the target device. The JTAG user code is an extension of theoption register. This data

FLEX6K_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target FLEX 6000device.Old NameCONF

FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICEAllows an EPC1 or EPC1441 configuration device to operate in a 3.3-V environment.TypeBooleanDevice Supp

GENERATE_HEX_FILEGenerates a Hexadecimal (Intel-format) Output File (.hexout) containing configuration data that can beprogrammed into a parallel data

GENERATE_RBF_FILEGenerates a Raw Binary File (.rbf) containing configuration data that an intelligent external controller canuse to configure the targ

GENERATE_TTF_FILEGenerates a Tabular Text File (.ttf) containing configuration data that an intelligent external controllercan use to configure the ta

HARDCOPYII_POWER_ON_EXTRA_DELAYDirects HardCopy chip to wait before INIT_DONE pin goes high and before the chip is in user mode.TypeEnumerationValues•

HEXOUT_FILE_COUNT_DIRECTIONSpecifies the count direction for the data in a Hexadecimal (Intel-Format) Output File (.hexout) as up ordown.Old NameHEX_F

OUTPUT_IO_TIMING_FAR_END_VMEASSpecifies, in volts, the measurement voltage at the far-end.TypeStringDevice SupportThis setting can be used in projects

HEXOUT_FILE_START_ADDRESSSpecifies the starting memory address for a Hexadecimal (Intel-Format) Output File (.hexout).TypeStringDevice SupportThis set

MAX7000S_JTAG_USER_CODESpecifies user-defined information about the target device. The JTAG user code is an extension of theoption register. This data

MAX7000_JTAG_USER_CODESpecifies user-defined information about the target device. The JTAG user code is an extension of theoption register. This data

MAX7000_USE_CHECKSUM_AS_USERCODESets the JTAG user code to match the checksum value of the device programming file. The programmingfile is a Programme

MERCURY_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target Mercurydevice.Old NameCONFI

MERCURY_CONFIG_DEVICE_JTAG_USER_CODESpecifies user-defined information about the configuration device. The JTAG user code is an extension ofthe option

MERCURY_JTAG_USER_CODESpecifies user-defined information about the target device. The JTAG user code is an extension of theoption register. This data

ON_CHIP_BITSTREAM_DECOMPRESSIONAllows the device to accept and decompress bitstreams during configuration. Produces compressedbitstreams and enables b

POF_VERIFY_PROTECTProtect configuration data in internal flash from being read through JTAGTypeBooleanDevice SupportThis setting can be used in projec

POR_SCHEMESpecifies device Power On Reset (POR) scheme.TypeEnumerationValues• Fast POR delay• Instant ON• Slow POR delayDevice SupportThis setting can

OUTPUT_IO_TIMING_NEAR_END_VMEASSpecifies, in volts, the measurement voltage at the near-end.TypeStringDevice SupportThis setting can be used in projec

RELEASE_CLEARS_BEFORE_TRI_STATESDirects the device to release the clear signal on registered logic cells and I/O cells before releasing theoutput enab

RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GNDReserves all unused pins on the target device in one of three states: as inputs that are tri-stated, or asoutputs

SECURITY_BITEnables the security bit support, which prevents a device from being examined and reprogrammed.TypeBooleanDevice SupportThis setting can b

STRATIXII_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target device.Old NameSTRATIX_II

STRATIXII_MRAM_COMPATIBILITYDirect Quartus II software to produce programming files that are compatible with both rev A and rev Bsilicon. This option

STRATIX_CONFIGURATION_DEVICESpecifies the configuration device that you want to use as the means of configuring the target device.Old NameYEAGER_CONFI

STRATIX_CONFIG_DEVICE_JTAG_USER_CODESpecifies user-defined information about the configuration device. The JTAG user code is an extension ofthe option

STRATIX_JTAG_USER_CODESpecifies user-defined information about the target device. The JTAG user code is an extension of theoption register. This data

USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENTLoads a checkered pattern as initial RAM content into all RAM blocks without specified RAM contentth

USE_CHECKSUM_AS_USERCODESets the JTAG user code to match the checksum value of the device programming file. The programmingfile is a Programmer Object

PCB_LAYERSpecifies which PCB layer the signal breaks out onTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device f

USE_CONFIGURATION_DEVICESpecifies that you intend to use a configuration device(s) such as the EPC2 as the means of configuring thetarget device. This

Assignment Group AssignmentsASSIGNMENT_GROUP_EXCEPTIONDefines a node(s) to be excluded as an excpetion to a previously added member. It can be an inst

ASSIGNMENT_GROUP_MEMBERDefines an element of a group. It can be an instance name or a wildcard representing multiple instancenamesTypeStringDevice Sup

Classic Timing AssignmentsANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTSDirects the Timing Analyzer to analyze latches as synchronous elements, rather than a

CUT_OFF_IO_PIN_FEEDBACKCuts off feedback from I/O pins during timing analysis. Cutting off I/O pin feedback is especially usefulwhen a bidirectional p

CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINSCuts the paths between registers clocked by unrelated clocks. This option makes the timing analysisreporting simila

CUT_OFF_READ_DURING_WRITE_PATHSCuts the path from the write enable register through the ESB to a destination register.TypeBooleanDevice SupportThis se

DEFAULT_HOLD_MULTICYCLEDetermines the default hold multicycle. The 'Same as Multicycle' setting ensures that the signal is latchedon the fin

DO_COMBINED_ANALYSISAnalyze both the fast corner (min delays) and the slow corner (max delays) and to report the results fromeach analysis.TypeBoolean

EMIF_SOC_PHYCLK_ADVANCE_MODELINGInstructs routing annotation to adjust the AV-SoC Phyclk delays.TypeBooleanDevice SupportThis setting can be used in p

PCB_LAYERSSpecifies the properties of all PCB layersTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.N

INPUT_TRANSITION_TIMESpecifies the input transition time. This assignment is used in Quartus to adjust the timing of the I/Obuffers for all families t

LVDS_FIXED_CLOCK_DATA_PHASESpecifies exact skew compensation. When the fixed clock-to-data skew is known, clock datasynchronization (CDS) can be pre-p

MAX_CORE_JUNCTION_TEMPThis is the maximum core junction temperature that will be encountered during operation. Specified indegrees CelsiusTypeStringDe

MIN_CORE_JUNCTION_TEMPThis is the minimum core junction temperature that will be encountered during operation. Specified indegrees CelsiusTypeStringDe

NOMINAL_CORE_SUPPLY_VOLTAGESpecifies the voltage for the core power supply. For Stratix III devices, the core supply voltage applies onlyto the VCCL p

PACKAGE_SKEW_COMPENSATIONIndicates that that the package skew for the signal has been compensated by the board trace delays.TypeBooleanDevice SupportT

PLL_EXTERNAL_FEEDBACK_BOARD_DELAYSpecifies an external board delay between a feedback output pin and a feedback input pin (fbin) for a PLLin external

TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORTInstructs the Fitter to aggressively optimize for hold timing closure.TypeBooleanDevice SupportThis setting can be u

TIMEQUEST_DO_CCPP_REMOVALDirects the TimeQuest Timing Analyzer to remove common clock path pessimism (CCPP) during slackcomputation.TypeBooleanDevice

TIMEQUEST_DO_REPORT_TIMINGDirects the TimeQuest Timing Analyzer to report the worst-case path per clock domain and analysis.TypeBooleanDevice SupportT

PCB_LAYER_THICKNESSThickness of the specific PCB layerTypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.

TIMEQUEST_MULTICORNER_ANALYSISDirects the TimeQuest Timing Analyzer to perform multicorner timing analysis, which analyzes thedesign against best-case

TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHSSpecifies the maximum number of worst-case timing paths for the TimeQuest Timing Analyzer to reportper clo

TIMEQUEST_REPORT_SCRIPTSpecifies the name of the tcl script that will be used to overwrite the default TimeQuest report panelscreated during a normal

TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSISDirects the TimeQuest Timing Analyzer to perform default timing analysis prior to running the user-spe

TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHSDirects the TimeQuest Timing Analyzer to report worst-case timing paths per clock domain and analysis.TypeBool

USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAINInstructs STA to take DLL frequency into account while calculating phase shift of DQS delay chainTypeBooleanDevic

Compiler AssignmentsALLOW_REGISTER_DUPLICATIONControls whether the Compiler is allowed to duplicate registers to improve design performance. Whenregis

ALLOW_REGISTER_MERGINGControls whether the Compiler is allowed to remove registers that are identical to other registers in thedesign. When register d

OPTIMIZATION_MODEControls the Compiler's high-level optimization strategy. By default, the Quartus II Compiler optimizes ina balanced mode, targe

TIMEQUEST2Controls whether the Compiler is allowed to use TimeQuest2 as its timing analysis engine.TypeEnumerationValues• FITTER_ONLY• OFF• ON• SIGNOF

SYNCHRONOUS_GROUPA logic option that assigns a synchronous group number for the specified node. This option directs theSSN Analyzer to view the specif

Design Assistant AssignmentsACLK_CATDirect Design Assistant to detect asynchronous clock domains on the design.TypeBooleanDevice SupportThis setting c

ACLK_RULE_IMSZER_ADOMAINDirect Design Assistant to detect improper synchronizer which moves data across asynchronous domainboundaries on the design.Ty

ACLK_RULE_NO_SZER_ACLK_DOMAINDirect Design Assistant to detect synchronizer between asynchronous clock domains on the design.TypeBooleanDevice Support

ACLK_RULE_SZER_BTW_ACLK_DOMAINDirect Design Assistant to detect synchronizer for every signal between asynchronous clock domains onthe design.TypeBool

CLK_CATDirect Design Assistant to check all clock-related violations on the design. Expand the items to turn offthe rule checking if irrelevant.TypeBo

CLK_RULE_CLKNET_CLKSPINESDirect Design Assistant to check clock net not mapped to clock spines used on the design.TypeBooleanDevice SupportThis settin

CLK_RULE_CLKNET_CLKSPINES_THRESHOLDSpecifies the threshold value for clock net not mapped to clock spines rule.TypeIntegerDevice SupportThis setting c

CLK_RULE_COMB_CLOCKDirect Design Assistant to check combinatorial logic output used as on-chip clock on the design.TypeBooleanDevice SupportThis setti

CLK_RULE_GATED_CLK_FANOUTDirect Design Assistant to check gated clock have feed to certain number of clock port to effectively savepower.TypeBooleanDe

CLK_RULE_INPINS_CLKNETDirect Design Assistant to check illegal input pins connected to clock net used on the design.TypeBooleanDevice SupportThis sett

Analysis & Synthesis AssignmentsADV_NETLIST_OPT_ALLOWEDSpecifies whether the Compiler should perform advanced netlist optimizations, such as gate-

CLK_RULE_INV_CLOCKDirect Design Assistant to check inverted clock used on the design.TypeBooleanDevice SupportThis setting can be used in projects tar

CLK_RULE_MIX_EDGESDirect Design Assistant to check mixed-clock edges used on the design.TypeBooleanDevice SupportThis setting can be used in projects

DA_CUSTOM_RULE_FILEUsed to set the path for DA custom rule fileTypeFile nameDevice SupportThis setting can be used in projects targeting any Altera de

DISABLE_DA_GX_RULEPrevents Design Assistant from running when the Fitter is running.TypeStringDevice SupportThis setting can be used in projects targe

DISABLE_DA_RULESuppress design assistant rule locally or turn off design assistant rule globally for general userTypeStringDevice SupportThis setting

DRC_DEADLOCK_STATE_LIMITSpecifies the maximum number of states that you want the Design Assistant to detect as a deadlockcondition. A larger number wi

DRC_DETAIL_MESSAGE_LIMITSpecifies the maximum number of detail messages that you want the Design Assistant to report.TypeIntegerDevice SupportThis set

DRC_FANOUT_EXCEEDINGSpecifies the minimum amount of fan-out that a node must have to be reported by the Design Assistant.TypeIntegerDevice SupportThis

DRC_GATED_CLOCK_FEEDSpecifies the minimum amount of clock port a gated clock must feed so that it's an acceptable gated clock.TypeIntegerDevice S

DRC_REPORT_FANOUT_EXCEEDINGDirects the Design Assistant to report all nodes with more than the specified amount of fan-out.TypeBooleanDevice SupportTh

BOARD_MODEL_EBD_SIGNAL_NAMESpecifies the Electronic Board Description (EBD) path description to be used with an I/O pin. You mustspecify the EBD file

ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAPSpecifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses thesetting specified

DRC_REPORT_TOP_FANOUTDirects the Design Assistant to report the specified number of nodes with the highest fan-out.TypeBooleanDevice SupportThis setti

DRC_TOP_FANOUTSpecifies the number of nodes with the highest fan-out that you want the Design Assistant to report.TypeIntegerDevice SupportThis settin

DRC_VIOLATION_MESSAGE_LIMITSpecifies the maximum number of violation messages that you want the Design Assistant to report.TypeIntegerDevice SupportTh

ENABLE_DA_RULEDesuppress design assistant rule locally or turn on design assistant rule globally for general userTypeStringDevice SupportThis setting

ENABLE_DRC_SETTINGSDirects the Design Assistant to run during a compilation based on user settings.TypeBooleanDevice SupportThis setting can be used i

FSM_CATDirect Design Assistant to detect finite state machine rules on the design.TypeBooleanDevice SupportThis setting can be used in projects target

FSM_RULE_DEADLOCK_STATEDirect Design Assistant to detect deadlock state in state machine on the design.TypeBooleanDevice SupportThis setting can be us

FSM_RULE_NO_RESET_STATEDirect Design Assistant to detect if reset state is specified for state machine on the design.TypeBooleanDevice SupportThis set

FSM_RULE_NO_SZER_ACLK_DOMAINDirect Design Assistant to detect synchronizer between asynchronous clock domains feeding to statemachine on the design.Ty

FSM_RULE_UNREACHABLE_STATEDirect Design Assistant to detect unreachable state in state machine on the design.TypeBooleanDevice SupportThis setting can

ALLOW_ANY_RAM_SIZE_FOR_RECOGNITIONAllows the Compiler to infer RAMs of any size, even if they don't meet the current minimumrequirements.TypeBool

FSM_RULE_UNUSED_TRANSITIONDirect Design Assistant to detect unused transition in state machine on the design.TypeBooleanDevice SupportThis setting can

HARDCOPY_FLOW_AUTOMATIONSpecifies which HardCopy flow will be run in HardCopy timing wizardTypeEnumerationValues• COMPILE_NEW_PROJECT• FULL_COMPILATIO

HARDCOPY_NEW_PROJECT_PATHSpecifies the directory path for the new/migrated HardCopy project.TypeStringDevice SupportThis setting can be used in projec

HCPY_CATDirect Design Assistant to detect HardCopy rules on the design. All HardCopy rules apply to HardCopydevices only.TypeBooleanDevice SupportThis

HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPESDirect Design Assistant to detect PLL that feeds multiple clock network types.TypeBooleanDevice SupportThis setting

HCPY_VREF_PINSDirect Design Assistant to detect VREF pins on the design. This rule applies to HardCopy devices only.TypeBooleanDevice SupportThis sett

NONSYNCHSTRUCT_CATDirect Design Assistant to check for non-synchronous design structures on the design.TypeBooleanDevice SupportThis setting can be us

NONSYNCHSTRUCT_RULE_ASYN_RAMDirects the Design Assistant to detect asynchronous memories targeted by the design. This rule applies toHardCopy devices

NONSYNCHSTRUCT_RULE_COMBLOOPDirect Design Assistant to check for combinatorial loop with unidentified function on the design.TypeBooleanDevice Support

NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WEDirect Design Assistant to detect combinatorial logic dirving asynchronous RAM Write Enable signals onthe design

ALLOW_ANY_ROM_SIZE_FOR_RECOGNITIONAllows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's currentminimum size req

NONSYNCHSTRUCT_RULE_DELAY_CHAINDirect Design Assistant to check for delay chain with unidentified function on the design.TypeBooleanDevice SupportThis

NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GENDirect Design Assistant to check illegal pulse generator on the design.TypeBooleanDevice SupportThis setting can

NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIEDDirect Design Assistant to detect latch of unidentified type on the design.TypeBooleanDevice SupportThis setting

NONSYNCHSTRUCT_RULE_MULTI_VIBRATORDirect Design Assistant to check multi-vibrator on the design.TypeBooleanDevice SupportThis setting can be used in p

NONSYNCHSTRUCT_RULE_REG_LOOPDirect Design Assistant to check for combinatorial loop with output of register feeding its own controlsignal on the desig

NONSYNCHSTRUCT_RULE_RIPPLE_CLKDirect Design Assistant to check ripple clock structure on the design.TypeBooleanDevice SupportThis setting can be used

NONSYNCHSTRUCT_RULE_SRLATCHDirect Design Assistant to detect SR-latch on the design.TypeBooleanDevice SupportThis setting can be used in projects targ

RESET_CATDirect Design Assistant to check reset-related violations on the design.TypeBooleanDevice SupportThis setting can be used in projects targeti

RESET_RULE_COMB_ASYNCH_RESETDirect Design Assistant to check combinatorial logic output used as on-chip asynchronous reset on thedesign.TypeBooleanDev

RESET_RULE_IMSYNCH_ASYNCH_DOMAINDirect Design Assistant to check for reset which is improperly synchronized in receiving asynchronousdomain on the des

ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITIONAllows the Compiler to infer shift registers of any size even if they do not meet the design's curre

RESET_RULE_IMSYNCH_EXRESETDirect Design Assistant to check improper synchronization of external reset on the design.TypeBooleanDevice SupportThis sett

RESET_RULE_UNSYNCH_ASYNCH_DOMAINDirect Design Assistant to check for reset which is not synchronized in receiving asynchronous domainon the design.Typ

RESET_RULE_UNSYNCH_EXRESETSuppress unsynchronized external reset rule.TypeBooleanDevice SupportThis setting can be used in projects targeting any Alte

SIGNALRACE_CATDirect Design Assistant to check signal race on the design.TypeBooleanDevice SupportThis setting can be used in projects targeting any A

SIGNALRACE_RULE_CLK_PORT_RACEDirect Design Assistant to check race condition between clock port and any other port of the sameregister.TypeBooleanDevi

SIGNALRACE_RULE_RESET_RACEDirect Design Assistant to detect synchronous port and asynchronous port of same register driven bysame signal sourceTypeBoo

SIGNALRACE_RULE_SECOND_SIGNAL_RACEDirect Design Assistant to detect more than one secondary signal of same register driven by same signalsourceTypeBoo

SIGNALRACE_RULE_TRISTATEDirect Design Assistant to detect Tri-state signal race conditionTypeBooleanDevice SupportThis setting can be used in projects

TIMING_CATDirect Design Assistant to check timing closure related violations on the design.TypeBooleanDevice SupportThis setting can be used in projec

EDA Netlist Writer AssignmentsEDA_BOARD_BOUNDARY_SCAN_OPERATIONSpecify the BSDL file operation either for pre-configuration or post-configurationTypeE

ALLOW_CHILD_PARTITIONSSpecifies whether or not an instance or a section of design hierarchy can contain user partitions.TypeBooleanDevice SupportThis

EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOLSpecifies the boundary scan format used for board level boundary scan testing.TypeStringDevice SupportThis setting

EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOLSpecifies the EDA third-party tool used for board level signal integrity analysis.TypeStringDevice SupportThis s

EDA_BOARD_DESIGN_SYMBOL_TOOLSpecifies the EDA third-party tool used for board level schematic design.TypeStringDevice SupportThis setting can be used

EDA_BOARD_DESIGN_TIMING_TOOLSpecifies the EDA third-party tool used for board level timing analysis.TypeStringDevice SupportThis setting can be used i

EDA_BOARD_DESIGN_TOOLSpecifies the EDA third-party tool used for board level design and analysis.TypeStringDevice SupportThis setting can be used in p

EDA_DESIGN_EXTRA_ALTERA_SIM_LIBSpecify additional ALTERA simulation model libraries required is used by the design filesTypeStringDevice SupportThis s

EDA_DESIGN_INSTANCE_NAMESpecify the instance name of the design in the test benchTypeStringDevice SupportThis setting can be used in projects targetin

EDA_ENABLE_GLITCH_FILTERINGWrite logic to filter glitches in the simulation netlist.TypeBooleanDevice SupportThis setting can be used in projects targ

EDA_ENABLE_IPUTF_MODEAllows you to simulate designs containing hw.tcl based IP cores. This may require adding .sip files to yourQuartus II project. Th

EDA_EXTRA_ELAB_OPTIONAdditional custom simulation elaboration options for one or more simulators.TypeStringDevice SupportThis setting can be used in p

ALLOW_POWER_UP_DONT_CARECauses registers that do not have a Power-Up Level logic option setting to power up with a don't carelogic level (X). A d

EDA_FLATTEN_BUSESFlattens all buses when creating the VHDL Output File (.vho). You should turn on this option if yourthird-party EDA environment does

EDA_FORMAL_VERIFICATION_ALLOW_RETIMINGAllow register retiming to be turned on for formal verificationTypeBooleanDevice SupportThis setting can be used

EDA_FORMAL_VERIFICATION_TOOLSpecifies the EDA third-party tool used for formal verification.TypeStringDevice SupportThis setting can be used in projec

EDA_FV_HIERARCHYDetermines how the hierarchy of design entities is to be processed during compilation. 'BLACKBOX'setting causes the entity t

EDA_GENERATE_FUNCTIONAL_NETLISTGenerate Verilog or VHDL netlist for functional simulation with EDA simulation tools. The SDF Timingfile (.sdo) is not

EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPTDirects the EDA Netlist Writer to generate a command script to run gate-level simulation with a third

EDA_GENERATE_POWER_INPUT_FILEGenerates a Power Input File (.pwf) to perform power analysis in the Quartus II software when usingthird-party simulation

EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPTDirects the EDA Netlist Writer to generate a command script to run RTL functional simulation with athird-par

EDA_GENERATE_TIMING_CLOSURE_DATAGenerates back-annotation data for performing in-place optimization with the LeonardoSpectrumsoftware.TypeBooleanDevic

EDA_IBIS_MODEL_SELECTOREnable or disable model selector feature for IBIS WriterTypeBooleanDevice SupportThis setting can be used in projects targeting

ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIESAllows the Compiler to take shift registers from different hierarchies of the design and put them in th

EDA_IBIS_MUTUAL_COUPLINGAllows you to print the per pin RLC package model with mutual coupling when generating IBIS OutputFiles (.ibs) with the EDA Ne

EDA_IBIS_SPECIFICATION_VERSIONSpecifies the IBIS Specification version.TypeEnumerationValues• 4p1• 4p2• 5p0Device SupportThis setting can be used in p

EDA_IPFS_FILESpecifies the library to which IPFS file should be compiledTypeFile nameDevice SupportThis setting can be used in projects targeting any

EDA_LAUNCH_CMD_LINE_TOOLAllows you to launch third-party EDA tools in the command-line mode rather than opening the graphicaluser interface.TypeBoolea

EDA_MAINTAIN_DESIGN_HIERARCHYMaintain the original user design hierarchy when generating Verilog or VHDL simulation netlist for theproject.TypeEnumera

EDA_MAP_ILLEGAL_CHARACTERSMaps the vertical bar (|), tilde (~), and colon (:) characters in Quartus II hierarchical node names to thelegal Verilog HDL

EDA_NATIVELINK_GENERATE_SCRIPT_ONLYAllows you to generate the script for a third-party EDA tool without running the EDA tool.TypeBooleanDevice Support

EDA_NATIVELINK_PORTABLE_FILE_PATHSSpecifies that the file paths in the generated third-party EDA tool command scripts should be written outusing relat

EDA_NATIVELINK_SIMULATION_SETUP_SCRIPTSpecify the script for EDA Tool. After compiling models, design files and test bench files, Native Link usesthis

EDA_NATIVELINK_SIMULATION_TEST_BENCHSpecify the active logical name of the test bench, that will be used to perform NativeLink SimulationTypeStringDev

ALLOW_SYNCH_CTRL_USAGEAllows the Compiler to utilize synchronous clear and/or synchronous load signals in normal mode logiccells. Turning on this opti

EDA_NETLIST_WRITER_OUTPUT_DIRSpecify the output directory for EDA Netlist WriterTypeFile nameDevice SupportThis setting can be used in projects target

EDA_RESYNTHESIS_TOOLSpecifies the EDA tool used for resynthesis.TypeStringDevice SupportThis setting can be used in projects targeting any Altera devi

EDA_RTL_SIMULATION_RUN_SCRIPTSpecifies the script file for performing RTL simulation using third-party simulation software.TypeFile nameDevice Support

EDA_RTL_SIM_MODEEnables the Advanced Options - VHDL or Verilog Simulation options for Test Bench mode orCommand/macro mode.TypeEnumerationValues• COMM

EDA_RTL_TEST_BENCH_FILE_NAMESpecifies the RTL simulation test bench file name for Test Bench Mode. File type can be a VHDL TestBench File (.vht), VHDL

EDA_RTL_TEST_BENCH_NAMESpecifies the name of top-level test bench in RTL simulation test bench file.TypeStringDevice SupportThis setting can be used i

EDA_RTL_TEST_BENCH_RUN_FORSpecifies the time duration for RTL simulation using third-party simulation.TypeTimeDevice SupportThis setting can be used i

EDA_SDC_FILE_NAMEName of Design Constraints file to be sourced in scripts generated for third party toolsTypeFile nameDevice SupportThis setting can b

EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLEDDisables setup and hold time violations detection in input registers of bi-directional pin

EDA_SIMULATION_RUN_SCRIPTSpecifies the script file for running a third-party simulation in Command/macro mode.TypeFile nameDevice SupportThis setting

ALLOW_XOR_GATE_USAGEAllows the Compiler to use the XOR gate that exists in a macrocell (that is, in an embedded cell within anEmbedded System Block [E

EDA_SIMULATION_TOOLSpecifies the third-party EDA tool used for simulation.TypeStringDevice SupportThis setting can be used in projects targeting any A

EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILESpecifies which type of output signals should be written out to the TCL file which can be used in a third

EDA_SIMULATION_VCD_OUTPUT_TCL_FILESpecifies whether or not a TCL file should be written out which can be used in a third-party EDAsimulation tool to g

EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAMESpecifies the name the TCL file should be written to which can be used in a third-party EDA simulationtool to g

EDA_TEST_BENCH_DESIGN_INSTANCE_NAMESpecifies the instance name of the design entity in the test bench file.TypeStringDevice SupportThis setting can be

EDA_TEST_BENCH_ENABLE_STATUSEnables the Advanced Options - VHDL or Verilog Simulation options for Test Bench mode orCommand/macro mode.TypeEnumeration

EDA_TEST_BENCH_ENTITY_MODULE_NAMESpecifies the top-level design entity in the test bench file.TypeStringDevice SupportThis setting can be used in proj

EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIBTells NativeLink to add extra simulation libraries to the specified module. This is required by the memorycontrolle

EDA_TEST_BENCH_FILEAssociates a test bench file with the logical test bench nameTypeFile nameDevice SupportThis setting can be used in projects target

EDA_TEST_BENCH_FILE_NAMESpecifies the test bench file name for Test Bench Mode. File type can be a VHDL Test Bench File (.vht),Verilog HDL Test Bench

APEX20K_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,minimize logic usa

EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARYSpecify the simulation library to which Gate Level Netlist will be compiledTypeStringDevice SupportThis setti

EDA_TEST_BENCH_MODULE_NAMEAssociates a test bench file with the logical test bench nameTypeStringDevice SupportThis setting can be used in projects ta

EDA_TEST_BENCH_NAMEDefine a logical name for test bench. Each test bench logical name has associated section, containing testbench information, and se

EDA_TEST_BENCH_RUN_FORSpecifies the simulation run time for a third-party simulation in Test Bench Mode.TypeTimeDevice SupportThis setting can be used

EDA_TEST_BENCH_RUN_SIM_FORSpecify the time interval for running EDA SimulationTypeTimeDevice SupportThis setting can be used in projects targeting any

EDA_TIME_SCALESpecifies the time unit used to represent timing delays in each Verilog Output File. The value for the TimeScale option may be between 0

EDA_TIMING_ANALYSIS_TOOLSpecifies the EDA third-party tool used for timing analysis.TypeStringDevice SupportThis setting can be used in projects targe

EDA_TRUNCATE_LONG_HIERARCHY_PATHSTruncate hierarchical node names to 80 characters.TypeBooleanDevice SupportThis setting can be used in projects targe

EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORYSpecify the directory where you store the library generated with the EDA Simulation Library Compilertool

EDA_VHDL_ARCH_NAMESpecify the name of Architecture in the generated VHDL simulation netlist.TypeStringDevice SupportThis setting can be used in projec

BOARD_MODEL_FAR_CSpecifies, in farads, the board trace model far capacitance.TypeStringDevice SupportThis setting can be used in projects targeting an

APEX20K_TECHNOLOGY_MAPPERSpecifies whether to target look-up table (LUT) or Product Term when implementing logic in the device.The Technology Mapper o

EDA_WAIT_FOR_GUI_TOOL_COMPLETIONSpecifies that NativeLink should wait for the EDA tool GUI launched by it to finish.TypeBooleanDevice SupportThis sett

EDA_WRITER_DONT_WRITE_TOP_ENTITYDo not write top-level entity in VHDL Output File (.vho).TypeBooleanDevice SupportThis setting can be used in projects

EDA_WRITE_DEVICE_CONTROL_PORTSAdd the devpor, devclrn, and devoe signals in the design as input ports in the top-level design hierarchy inthe Verilog

EDA_WRITE_NODES_FOR_POWER_ESTIMATIONWrite script for Simulation tool to generate VCD file for outputs for power estimation.TypeEnumerationValues• ALL_

Equivalence Checker AssignmentsEQC_AUTO_BREAK_CONEEnable EQC for auto cone break when compare is abort.TypeBooleanDevice SupportThis setting can be us

EQC_AUTO_COMP_LOOP_CUTEnable EQC for auto cut comp loop.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device fami

EQC_AUTO_INVERSIONEnable EQC for auto check inversion level.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device

EQC_AUTO_PORTSWAPEnable EQC auto swap the port.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Syntax

EQC_AUTO_TERMINATEEnable auto terminates when conclusion(not equivalent or undecided) is met.TypeBooleanDevice SupportThis setting can be used in proj

EQC_BBOX_MERGEEnable EQC automatic merge black box.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Sy

AUTO_CARRY_CHAINSAllows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers into thedesign. This option is also required

EQC_CONSTANT_DFF_DETECTIONEnable EQC automatic constant DFF detectionTypeBooleanDevice SupportThis setting can be used in projects targeting any Alter

EQC_DETECT_DONT_CARESEnable EQC detect don't cares.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device fami

EQC_DFF_SS_EMULATIONEnable EQC DFF secondary signal emulation.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera devic

EQC_DUPLICATE_DFF_DETECTIONEnable EQC automatic duplicate DFF detectionTypeBooleanDevice SupportThis setting can be used in projects targeting any Alt

EQC_LVDS_MERGEEnable EQC automatic merge LVDS.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Syntax

EQC_MAC_REGISTER_UNPACKEnable EQC for auto unpack MAC register.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera devi

EQC_PARAMETER_CHECKEnable EQC check parameter.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Syntax

EQC_POWER_UP_COMPAREEnable EQC for comparing on the power-up level .TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera

EQC_RAM_REGISTER_UNPACKEnable EQC for auto unpack RAM register.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera devi

EQC_RAM_UNMERGINGEnable EQC automatic unmerge RAM.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Syn

AUTO_CASCADE_CHAINSAllows the Compiler to create cascade chains automatically by inserting CASCADE buffers into thedesign. The length of the chains is

EQC_RENAMING_RULESEnable EQC use renaming rules.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Synta

EQC_RENAMING_RULES_LISTStore eqc renaming rulesTypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesTh

EQC_SET_PARTITION_BB_TO_VCC_GNDEnable EQC for set partition Black-box unconnected input to VCC or GND.TypeBooleanDevice SupportThis setting can be use

EQC_SHOW_ALL_MAPPED_POINTSEnable EQC show all mapped points.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device

EQC_STRUCTURE_MATCHINGEnable EQC for map using structure matching.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera d

EQC_SUB_CONE_REPORTEnable EQC show sub cone report.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Sy

Fitter AssignmentsACTIVE_SERIAL_CLOCKSpecifies the clock source for Fast Active Serial programming.TypeEnumerationValues• CLKUSR• FREQ_100MHz• FREQ_12

ADCE_ENABLEDTo disable ADCE on a PMA direct channel for RX PMA. Setting this option to Off will disable ADCE.Setting this option to Auto will leave th

ADVANCED_PHYSICAL_OPTIMIZATIONEnable Advanced Physical Optimization to improve the quality of results with more consistent timingclosure.TypeBooleanDe

ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFERSpecifies whether the Fitter allows input pins with LVTTL or LVCMOS I/O standards to be place

AUTO_CLOCK_ENABLE_RECOGNITIONAllows the Compiler to find logic that feeds a register and move the logic to the register's clock enableinput port.

ALM_REGISTER_PACKING_EFFORTThis guides how aggressively the Fitter will pack ALMs when trying to place registers into desired LABlocations. Specifical

ALWAYS_ENABLE_INPUT_BUFFERSEnables input buffers on all I/O pins including output pins. This option is required for the SAMPLE/PRELOAD JTAG instructio

APEX20KE_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.TypeStringDevice SupportThis setting can be use

APEX20K_CONFIGURATION_SCHEMEThe method used to load data into the device. Three configuration schemes are available: Passive ParallelAsynchronous (PPA

APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLSDecreases the propagation delay from an input or bidirectional pin to logic and embedded cells within th

APEX20K_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.Old NameDEVICE_IO_STANDARDTypeStringDevice Suppo

APEXII_CONFIGURATION_SCHEMEThe method used to load data into the device. Three configuration schemes are available: Passive ParallelAsynchronous (PPA)

APEXII_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.Old NameAPEX20KF_DEVICE_IO_STANDARDTypeStringDevi

ASYNC_PIPELINE_DISABLE_DESTINATION_CHECKAllows the Automatic Asynchronous Signal Pipelining algorithm to run on the specified asynchronoussignal even

ASYNC_PIPELINE_REG_REACHSpecify the maximum number of LABs that the asynchronous signal sourcing at the To register can goacross before a new pipeline

AUTO_DSP_RECOGNITIONAllows the Compiler to find a multiply-accumulate function or a multiply-add function that can bereplaced with the altmult_accum o

AUTO_C3_M9K_BIT_SKIPDirects the fitter to skip certain bitlines in Cyclone III (including LS) M9K blocks that may be susceptibleto read bit error when

AUTO_DELAY_CHAINSAllows the Fitter to choose the optimal delay chain to meet tsu and tco timing requirements for all I/Oelements. Turning on this opti

AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINSAllows the Fitter to choose how to optimize the delay chains for high fanout input pins. You must enableth

AUTO_GLOBAL_CLOCKAllows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clocksignal that is made available

AUTO_GLOBAL_MEMORY_CONTROLSAllows the Compiler to choose the signals that feed the most write enable and read enable inputs tomemories as global write

AUTO_GLOBAL_OEAllows the Compiler to choose the signal that feeds the most TRI buffers as a global output enable signalthat is made available througho

AUTO_GLOBAL_REGISTER_CONTROLSAllows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excludingclock signals)

AUTO_MERGE_PLLSAllows the Compiler to automatically find and merge together two compatible phase-locked loops (PLL)driven by the same clock source, re

AUTO_PACKED_REGISTERS_MAXAllows the Compiler to automatically implement a register and a combinational function in the samelogic cell. This option con

Default ValueAutoMNL-Q210052015.05.04AUTO_PACKED_REGISTERS_MAX449Quartus Settings File Reference ManualAltera CorporationSend Feedback

AUTO_ENABLE_SMART_COMPILESpecifies whether the SignalTap II Logic Analyzer should perform a smart compilation if conditions existin which SignalTap II

AUTO_TURBO_BITControls the speed vs. power usage trade-off for a macrocell. If the Turbo Bit is on, the macrocell's speedincreases; if it is off,

BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICEDirects the Compiler to base the Pin-Out File (.pin) and floorplan package views on the largest selectedSameFrame

BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIESControls whether RAMs implemented in MLAB cells must have equivalent pause read capabilities asR

BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONSControls whether RAMs implemented in MLAB cells must have equivalent power up conditions as RAMsimple

BLOCK_RAM_TO_MLAB_CELL_CONVERSIONControls whether the fitter is able to convert RAMs to use LAB locations when those RAMs use 'Auto' asthe s

C3_M9K_BIT_SKIPDirects the fitter to skip certain bitlines in Cyclone III M9K blocks when implementing the specificedRAM or ROM cell. The default rema

CARRY_OUT_PINS_LCELL_INSERTDirects the Fitter to enable or disable logic cell insertion when the I/Os are fed by carry or cascade chains.When this opt

CDR_BANDWIDTH_PRESETSpecifies the CDR (clock data recovery) bandwidth preset setting.TypeEnumerationValues• Auto• High• Low• MediumDevice SupportThis

CKN_CK_PAIRSpecifies the pairing of a CKn pin to a CK pin. The I/O pin of a CK CKn pair must be placed on adifferential pin pair. This option is ignor

CLAMPING_DIODETurns on the Clamping Diode of a pin. The clamping diode can be turned on to limit overshoot voltagefor a pin in input operation. The cl

AUTO_GLOBAL_CLOCK_MAXAllows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clocksignal that is made avail

CLOCK_ENABLE_ROUTINGSpecifies whether a clock enable signal in an I/O cell should be driven by the peripheral bus or the single-pin path. The Single-P

CLOCK_REGIONSpecifies that a signal routed using global routing paths should use the specified clock region. Valid valuesare in the form \"Region

CLOCK_TO_OUTPUT_DELAYSpecifies the propagation delay to the output or bidirectional pin from the output register implemented inan I/O cell. This is an

CONFIGURATION_VCCIO_LEVELSpecifies the VCCIO voltage of the configuration pins for the current configuration scheme on the targetdevice.TypeStringDevi

CRC_ERROR_CHECKINGSpecifies error detection CRC usage for the selected device. If error detection CRC is turned on, the devicechecks the validity of t

CRC_ERROR_OPEN_DRAINSpecify open drain on the CRC Error pin should be enabled or notTypeBooleanDevice SupportThis setting can be used in projects targ

CURRENT_STRENGTH_NEWSets the drive strength of a pin. Specify a number (in mA), MIN, or MAX for output or bidirectional pinsthat support programmable

CVP_CONFDONE_OPEN_DRAINSpecify open drain on the CvP_CONFDONE pin should be enabled or notOld NameCVPCIE_CONFDONE_OPEN_DRAINTypeBooleanDevice SupportT

CVP_MODESpecifies the configuration mode for Configuration via Protocol (CvP).Old NameCVPCIE_MODETypeEnumerationValues• Core initialization• Core init

CYCLONEIII_CONFIGURATION_SCHEMEThe method used to load data into the device. Up to four configuration schemes are available, dependingon the selected

AUTO_GLOBAL_OE_MAXAllows the Compiler to choose the signal that feeds the most TRI buffers as a global output enable signalthat is made available thro

CYCLONEII_CONFIGURATION_SCHEMEThe method used to load data into the device. Two configuration schemes are available: Passive Serial(PS); and Active Se

CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATIONSpecifies how the nCEO pin should be used when the device is operating in user mode after configurationis co

CYCLONEII_TERMINATIONAllows the Compiler to configure the on-chip termination (OCT) and impedance matching for an I/Opin. OCT helps to prevent signal

CYCLONE_CONFIGURATION_SCHEMEThe method used to load data into the device. Two configuration schemes are available: Passive Serial(PS); and Active Seri

D1_DELAYSpecifies the propagation delay for D1 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, check

D1_FINE_DELAYEnable the fine delay resolution on D1 DelayOld NameT1_FINE_DELAYTypeBooleanDevice SupportThis setting can be used in projects targeting

D2_DELAYSpecifies the propagation delay for D2 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, check

D3_DELAYSpecifies the propagation delay for D3 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, check

D4_DELAYSpecifies the propagation delay for D4 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, check

D4_FINE_DELAYEnable the fine delay resolution on D4 DelayOld NameT7_FINE_DELAYTypeBooleanDevice SupportThis setting can be used in projects targeting

AUTO_IMPLEMENT_IN_ROMAllows the Compiler to automatically implement combinatorial logic in ROM (that is, in an embeddedcell within an Embedded System

D5_DELAYSpecifies the propagation delay for D5 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, check

D5_FINE_DELAYEnable the fine delay resolution on D5 DelayOld NameT9_FINE_DELAYTypeBooleanDevice SupportThis setting can be used in projects targeting

D5_OCT_DELAYSpecifies the propagation delay for D5 OCT Delay Cell. This is an advanced option that should be usedonly after you have compiled a projec

D5_OE_DELAYSpecifies the propagation delay for D5 Output-Enable Delay Cell. Use this advanced option only after youhave compiled a project, checked th

D6_DELAYSpecifies the propagation delay for D6 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, check

D6_FINE_DELAYEnable the fine delay resolution on D6 DelayOld NameT10_FINE_DELAYTypeBooleanDevice SupportThis setting can be used in projects targeting

D6_OCT_DELAYSpecifies the propagation delay for D6 OCT Delay Cell. This is an advanced option that should be usedonly after you have compiled a projec

D6_OE_DELAYSpecifies the propagation delay for D6 Output-Enable Delay Cell. This is an advanced option that shouldbe used only after you have compiled

D6_OE_FINE_DELAYEnable the fine delay resolution on D6 Output-Enable DelayOld NameT10_OE_FINE_DELAYTypeBooleanDevice SupportThis setting can be used i

DATA0_PINSpecifies the Data[0] configuration pin.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Note

AUTO_LCELL_INSERTIONAllows the Compiler to insert macrocells into the design. This option is ignored if it is assigned toanything other than a design

DCLK_PINSpecifies the DCLK configuration pin.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThi

DC_CURRENT_FOR_ELECTROMIGRATION_CHECKSpecifies the maximum amount of DC current, in mA, allowed when the Fitter checks forelectromigration violations.

DDIO_INPUT_REGISTERDirects the Compiler to perform special placement and routing of the specified register to prevent registerpacking of the input reg

DDIO_OUTPUT_REGISTERDirects the Compiler to perform special placement and routing of the specified register to provide aglitch-free output. This is us

DDIO_OUTPUT_REGISTER_DISTANCEDirects the Fitter to place the DDIO output registers (and output mux) that feed this I/O pin in a locationwhose LAB dist

DECREASE_INPUT_DELAY_TO_INPUT_REGISTERDecreases the propagation delay from an input pin to the data input of the input register implemented inthe I/O

DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTERDecreases the propagation delay from the interior of the device to the data input of the output registerimpleme

DELAY_SETTING_FROM_VIO_TO_COREIncreases the propagation delay from a vertical pin to the interior of the device when the vertical pin isusing the Fast

DEVICESpecifies the device to use.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThe value of th

DEVICE_INITIALIZATION_CLOCKSpecifies the clock source for device initialization (the duration between CONF_DONE signal went highand before INIT_DONE s

BOARD_MODEL_FAR_DIFFERENTIAL_RSpecifies, in ohms, the board trace model far differential resistance.TypeStringDevice SupportThis setting can be used i

AUTO_OPEN_DRAIN_PINSAllows the Compiler to automatically convert a tri-state buffer with a strong low data input into theequivalent open-drain buffer.

DEVICE_MIGRATION_LISTShows the selected migration devices for the current device.TypeStringDevice SupportThis setting can be used in projects targetin

DEVICE_TECHNOLOGY_MIGRATION_LISTShows the selected technology migration devices for the current device.TypeStringDevice SupportThis setting can be use

DM_PINSpecifies the DM pin. The DM pin of a DQS group must be placed in the DM pin location of the DQSgroup. This option is ignored if is assigned to

DPRIO_CHANNEL_NUMRX/TX channel number for DPRIO logicTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.

DPRIO_CRUCLK_NUMLogical RX CRU clock numberTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.NotesNoneS

DPRIO_INTERFACE_REGInterface input/output register of DPRIO logicTypeBooleanDevice SupportThis setting can be used in projects targeting any Altera de

DPRIO_QUAD_NUMRX/TX quad number for DPRIO logicTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.NotesN

DPRIO_QUAD_PLL_NUMLogical CMU PLL number in a quadTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.Not

DPRIO_TX_PLL0_REFCLK_NUMLogical TX PLL0 Refclk numberTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.

DPRIO_TX_PLL1_REFCLK_NUMLogical TX PLL1 Refclk numberTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.

AUTO_PARALLEL_EXPANDERSAllows the Compiler to automatically create chains of parallel expander product terms. Parallel expandersare available in macro

DPRIO_TX_PLL_NUMLogical TX PLL numberTypeIntegerDevice SupportThis setting can be used in projects targeting any Altera device family.NotesNoneSyntax

DQSB_DQS_PAIRSpecifies the pairing of a DQSn pin to a DQS pin. The I/O pin of a DQS must be placed in the DQS pinlocation of a DQS group; the I/O pin

DQSOUT_DELAY_CHAINSet the propagation delay on the DQSBUS signal from the DQS pin. This is an advanced option thatshould be used only after you have c

DQS_ENABLE_DELAY_CHAINSet the propagation delay on the DQS enable signal for the DQS pin. This is an advanced option thatshould be used only after you

DQS_LOCAL_CLOCK_DELAY_CHAINSet the propagation delay on the DQS signal to the input register of the target pin. This is an advancedoption that should

DQ_GROUPSpecifies the grouping from a DQS pin to its associated DQ pins and the width (4, 9, 18, or 36) of thegroup. Setting this option allows the Fi

DQ_PINDesignates the specified pin as a DQ I/O pin.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.No

DUAL_PURPOSE_CLOCK_PIN_DELAYSpecifies the propagation delay from a dual-purpose clock pin to its fan-out destinations that are routedon the global clo

DUPLICATE_ATOMDirects the Compiler to duplicate the source node, and uses the new duplicate node to fan out to thedestination node; the original sourc

DYNAMIC_OCT_CONTROL_GROUPAssigns a dynamic termination control group number for the specified node. Turning on this optiondirects the Fitter to view t

AUTO_PARALLEL_SYNTHESISOption to enable/disable automatic parallel synthesis. This option can be used to speed up synthesiscompile time by using multi

ECO_ALLOW_ROUTING_CHANGESThis option controls whether the Fitter will move items in a design to ensure that new ECO signals getrouted.TypeBooleanDevic

ECO_OPTIMIZE_TIMINGControls whether the fitter optimizes to meet the user's maximum delay timing requirements (eg. clockcycle time, Tsu, Tco) dur

ECO_REGENERATE_REPORTControls whether the fitter report is regenerated during ECO compiles. By default, this option is set to off.Turning it on will r

ENABLE_ASMI_FOR_FLASH_LOADEREnables ASMI interface for Flash Loader even before condone goes high.TypeBooleanDevice SupportThis setting can be used in

ENABLE_BENEFICIAL_SKEW_OPTIMIZATIONAllows the fitter to insert skew on globally routed clock signals to improve the performance of the design.TypeBool

ENABLE_BOOT_SEL_PINEnables CONFIG_SEL pin in user mode. If this option is turned off, the CONFIG_SEL pin are disabledwhen the device operates in user

ENABLE_BUS_HOLD_CIRCUITRYEnables bus-hold circuitry during device operation. If this option is turned on, a pin will retain its lastlogic level when i

ENABLE_CONFIGURATION_PINSEnables major configuration pins, nCONFIG, nSTATUS, and CONF_DONE pin in user mode. If thisoption is turned off, the nCONFIG,

ENABLE_CRC_ERROR_PINSpecifies error detection CRC and CRC_ERROR pin usage for the selected device. If error detection CRCis turned on, the device chec

ENABLE_CVP_CONFDONEEnable the CvP_CONFDONE pin, which indicates that the device finished core programming inConfiguration via Protocol mode. If this o

AUTO_RAM_BLOCK_BALANCINGEnables the Compiler to automatically use different memory types when using auto RAM blocks andallows the Compiler to use diff

ENABLE_DEVICE_WIDE_OEEnables the DEV_OE pin when the device is in user mode. If this option is turned on, all outputs on thechip operate normally. Whe

ENABLE_DEVICE_WIDE_RESETEnables the DEV_CLRn pin, which allows all registers of the device to be reset by an external source. Ifthis option is turned

ENABLE_HOLD_BACK_OFFEnables the Fitter to successfully fit a design despite infeasible hold constraints.TypeEnumerationValues• Off• OnDevice SupportTh

ENABLE_INIT_DONE_OUTPUTEnables the INIT_DONE pin, which allows you to externally monitor when initialization is completedand the device is in user mod

ENABLE_JTAG_BST_SUPPORTEnables JTAG boundary-scan test (BST) support.TypeBooleanDevice SupportThis setting can be used in projects targeting any Alter

ENABLE_JTAG_PIN_SHARINGEnables JTAG pins sharing feature. JTAGEN pin is enabled and become dedicated input pin in usermode. JTAG pins (TDO, TCK, TDI,

ENABLE_NCEO_OUTPUTEnables the nCEO pin. This pin should be connected to the nCE of the succeeding device when multipledevices are being programmed. If

ENABLE_NCE_PINEnables nCE pin in user mode. If this option is turned off, the nCE pin are disabled when the deviceoperates in user mode and is availab

ENABLE_NCONFIG_FROM_COREEnables the nCONFIG signal from the core. If this option is turned on, you can send the nCONFIG signalfrom the core or the pac

ENABLE_PR_PINSAllows you to enable the PR_REQUEST, PR_READY, PR_ERROR, PR_DONE, DCLK, and DATA[15..0]pins. These pins are needed to support partial re

AUTO_RAM_RECOGNITIONAllows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or thelpm_ram_dp megafunction. T

ENABLE_VREFA_PINEnable the circuitry for input voltage reference pins A.Old NameEnable VREFA pinTypeBooleanDevice SupportThis setting can be used in p

ENABLE_VREFB_PINEnable the circuitry for input voltage reference pins B.Old NameEnable VREFB pinTypeBooleanDevice SupportThis setting can be used in p

ERROR_CHECK_FREQUENCY_DIVISORSpecifies the divide value of the internal clock, which determines the frequency of the CRC. The dividevalue must be a po

EXCLUSIVE_IO_GROUPAssigns an exclusive group number for the specified I/O. I/Os with the different exclusive group numbercannot share the same bank.Ty

EXTERNAL_FLASH_FALLBACK_ADDRESSSpecifies the fallback image location address in EPCQ configuration device when external fallback isenabled.TypeStringD

EXTERNAL_LVDS_RX_USES_DPAIndicates that this LVDS Transmitter pin is connected to an external LVDS Receiver that uses DPA.TypeBooleanDevice SupportThi

FALLBACK_TO_EXTERNAL_FLASHDuring power up, if the default internal configuration image is corrupted, the device will look for primaryfallback image in

FASTROW_INTERCONNECTUses FastRow interconnect to route the fan-outs of an input or bidirectional pin. Both the pin and its fan-out(s) must also be ass

FINAL_PLACEMENT_OPTIMIZATIONSpecifies whether the Fitter performs final placement optimizations. Performing final placementoptimizations may improve t

FITTER_ADJUST_HC_SHORT_PATH_GUARDBANDAllows timing analysis to add extra short path guardband on a specific node during fitting.TypeIntegerDevice Supp

AUTO_RAM_TO_LCELL_CONVERSIONAllows the Compiler to convert small RAM blocks into logic cells.TypeBooleanDevice SupportThis setting can be used in proj

FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATIONSpecifies whether the Fitter aggressively optimizes for routability. Performing aggressive routabilityoptimi

FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGINSpecifies the amount of worst-case slack margin the fitter should try to maintain when the Fitter Effortoption

FITTER_EARLY_TIMING_ESTIMATE_MODEControls the type of early timing estimate produced by the Early Timing Estimate feature. Realistic willestimate the

FITTER_EFFORTControls the fitter's trade-off between performance and compilation speed. Auto Fit adjusts the fitteroptimization effort to minimiz

FIT_ATTEMPTS_TO_SKIPControls how many fit attempts the Fitter skips. In subsequent fit attempts, the Fitter uses higher effort toimprove design routab

FIT_ONLY_ONE_ATTEMPTControls how many fitting attempts the fitter tries to get a fit. When this option is off (default), the fittertries a maximum of

FLEX10K_CONFIGURATION_SCHEMEThe method used to load data into the device. Three configuration schemes are available: Passive ParallelAsynchronous (PPA

FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLSDecreases the propagation delay from an input or bidirectional pin to logic and embedded cells within th

FLEX10K_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.TypeStringDevice SupportThis setting can be used

FLEX10K_ENABLE_LOCK_OUTPUTEnables the lock output, which is available in devices with ClockLock phase-locked loop circuitry. Thelock output monitors w

AUTO_RESOURCE_SHARINGAllows the Compiler to share hardware resources among many similar, but mutually exclusive, operationsin your HDL source code. If

FLEX10K_MAX_PERIPHERAL_OESets the limit on the number of peripheral OE buses that can be used.TypeIntegerDevice SupportThis setting can be used in pro

FLEX6K_CONFIGURATION_SCHEMEThe method used to load data into the device. Two configuration schemes are available: Passive Serial(PS) and Passive Seria

FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLSDecreases the propagation delay from an input or bidirectional pin to logic and embedded cells within the

FLEX6K_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.TypeStringDevice SupportThis setting can be used

FORCE_CONFIGURATION_VCCIOForces the VCCIO voltage of the configuration pins to be the same as the configuration device I/Ovoltage.TypeBooleanDevice Su

FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGSDirects the Fitter to treat periphery placement warnings as errors. As a result, the Fitter attempts

FORCE_FRACTURED_MODE_ALM_IMPLEMENTATIONDirects the fitter to implement the specified node using the fractured mode of the ALM. This assignmentwill onl

FORCE_MERGE_PLLForces the slave PLL to be merged with the master PLL. This option should be used only for twocompatible PLLs driven by the same clock

FORCE_MERGE_PLL_FANOUTSForces the fanouts of the slave PLL clock output to be merged into the master PLL clock output. Thisoption should be used only

FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATIONDirects the fitter to implement the specified node using the non-fractured mode of the ALM. Thisassignment

AUTO_ROM_RECOGNITIONAllows the Compiler to find logic that can be replaced with the altsyncram or the lpm_rom megafunction.Turning on this option may

FORM_DDR_CLUSTERING_CLIQUEAllows the Fitter to form cluster cliques on a specific DDR logic structure, which may lead to betterplacement result and im

GENERATE_GXB_RECONFIG_MIFGenerates a GXB reconfig MIF file for each used GXB Transmitter and Receiver channel pair (Stratix IIGX and Arria GX) or each

GENERATE_GXB_RECONFIG_MIF_WITH_PLLGenerates a GXB reconfig MIF file with PLL data for each used GXB Transmitter and Receiver channelpair. Reprogrammin

GLOBAL_SIGNALSpecifies whether the signal should be routed using global routing paths. Global signals can be both pin-and logic-driven, and can be any

GLOBAL_SIGNAL_CLKCTRL_LOCATIONSpecifies the CLKCTRL that the signal should be routed using global routing paths. The value to use is thesame as that u

GNDIO_CURRENT_1PT8VFor user to override GNDIO current of 1.8-V io standard. Original current is 2mATypeIntegerDevice SupportThis setting can be used i

GNDIO_CURRENT_2PT5VFor user to override GNDIO current of 2.5-V io standard. Original current is 2mATypeIntegerDevice SupportThis setting can be used i

GNDIO_CURRENT_GTLFor user to override GNDIO current of GTL. Not yet supported in MAX7000.TypeIntegerDevice SupportThis setting can be used in projects

GNDIO_CURRENT_GTL_PLUSFor user to override GNDIO current of GTL+. Original current is 50mATypeIntegerDevice SupportThis setting can be used in project

GNDIO_CURRENT_LVCMOSFor user to override GNDIO current of LVCMOS. Original current is 2mATypeIntegerDevice SupportThis setting can be used in projects

AUTO_SHIFT_REGISTER_RECOGNITIONAllows the Compiler to find a group of shift registers of the same length that can be replaced with thealtshift_taps me

GNDIO_CURRENT_LVTTLFor user to override GNDIO current of LVTTL. Original current is 4mATypeIntegerDevice SupportThis setting can be used in projects t

GNDIO_CURRENT_PCIFor user to override GNDIO current of PCI. Original current is 4mATypeIntegerDevice SupportThis setting can be used in projects targe

GNDIO_CURRENT_SSTL2_CLASS1For user to override GNDIO current of SSTL2_CLASS1. Original current is 14mATypeIntegerDevice SupportThis setting can be use

GNDIO_CURRENT_SSTL2_CLASS2For user to override GNDIO current of SSTL2_CLASS2. Original current is 21mATypeIntegerDevice SupportThis setting can be use

GNDIO_CURRENT_SSTL3_CLASS1For user to override GNDIO current of SSTL3_CLASS1. Original current is 18mATypeIntegerDevice SupportThis setting can be use

GNDIO_CURRENT_SSTL3_CLASS2For user to override GNDIO current of SSTL3_CLASS2. Original current is 25mATypeIntegerDevice SupportThis setting can be use

GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIMEControls whether the fitter tries to achieve a zero hold time for I/O pins that feed globally clockedregis

GXB_0PPM_CLOCK_GROUPSpecifies a group of GXB core clocks that have zero(0) PPM difference. The clock driver source specifiedin the GXB 0 PPM clock gro

GXB_0PPM_CLOCK_GROUP_DRIVERSpecifies core clocks that have zero PPM difference. Follow the Altera High Speed I/O ApplicationsTechnical Support recomme

GXB_0PPM_CORECLKSpecifies core clocks that have zero PPM difference. Follow the Altera High Speed I/O ApplicationsTechnical Support recommendations wh

BLOCK_DESIGN_NAMINGSpecify the naming scheme used for the block design. This option is ignored if it is assigned to anythingother than a design entity

GXB_0PPM_CORE_CLOCKSpecifies two GXB core clocks that have zero (0) PPM difference. The core clock driver for the assignmentsource GXB must have a dif

GXB_CLOCK_GROUPSpecifies GXB core clock groups to be merged after compilation. All specified GXB transmitters in theGXB shared clock group are driven

GXB_CLOCK_GROUP_DRIVERSpecifies the GXB core clock driver that drives all core clocks in a GXB shared clock group aftercompilation. All GXB transmitte

GXB_RECONFIG_GROUPSpecifies whether GXB transceiver channels with Dynamic Reconfiguration can be placed in the samephysical channel. GXB receivers and

GXB_RECONFIG_MIFSpecifies the MIF file name to store the GXB reconfig channel data for the entire GXB Receiver orTransmitter channel. This setting can

GXB_RECONFIG_MIF_PLLIncludes PLL info in the GXB reconfig channel data.TypeBooleanDevice SupportThis setting can be used in projects targeting any Alt

GXB_REFCLK_COUPLING_TERMINATION_SETTINGAllows the Compiler to configure the AC/DC coupling and on-chip termination (OCT) for a Stratix II GXgigabit tr

GXB_RESERVED_TRANSMIT_CHANNELSpecifies that a transmitter channel is a reserved transmit channel.TypeBooleanDevice SupportThis setting can be used in

GXB_TX_PLL_RECONFIG_GROUPSpecifies whether GXB transceiver channels with Dynamic TX PLL Reconfiguration can be placed in thesame physical GXB Quad. If

HPS_IOFlags an I/O in the user netlist as one that is intended to be owned by a HPS block.TypeBooleanDevice SupportThis setting can be used in project

BOARD_MODEL_FAR_PULLDOWN_RSpecifies, in ohms, the board trace model far pull-down resistance.TypeStringDevice SupportThis setting can be used in proje

CARRY_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of both user-entered and Compiler-synthesizedCARRY_SUM buffers. Carry chains that

IGNORE_MODE_FOR_MERGEIgnores the mode of the PLL when the Fitter attempts to merge PLLs, therefore allowing PLLs withdifferent modes to be merged.Type

IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODEAllows you to specify the MLAB memory blocks implementation mode. MLAB memory blocks areimplemented in 32-bit deep m

INCREASE_DELAY_TO_OUTPUT_ENABLE_PINIncreases the propagation delay to the output enable pin from internal logic or the output enable registerimplement

INCREASE_DELAY_TO_OUTPUT_PINIncreases the propagation delay to the output or bidirectional pin from the output register implementedin an I/O cell. Thi

INCREASE_INPUT_CLOCK_ENABLE_DELAYIncreases the propagation delay from the interior of the device to the clock enable input of an outputregister. This

INCREASE_INPUT_DELAY_TO_CE_IO_REGISTERIncreases the propagation delay from the interior of the device to the clock enable input of an I/O register.Thi

INCREASE_OUTPUT_CLOCK_ENABLE_DELAYIncreases the propagation delay from the interior of the device to the clock enable input of an outputregister. This

INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYIncreases the propagation delay from the interior of the device to the clock enable input of an outputenable

INCREASE_TZX_DELAY_TO_OUTPUT_PINSupports zero bus-turnaround (ZBT) by increasing the propagation delay of the falling edge of the outputenable signal.

INC_PLC_MODEDirects the Quartus II software to run in Incremental Placement Mode.TypeBooleanDevice SupportThis setting can be used in projects targeti

CASCADE_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of both user-entered and Compiler-synthesizedCASCADE buffers. Cascade chains tha

INIT_DONE_OPEN_DRAINSpecify open drain on the INIT_DONE pin should be enabled or notTypeBooleanDevice SupportThis setting can be used in projects targ

INPUT_DELAY_CHAINSpecifies the propagation delay for Input Delay Chain. This is an advanced option that should be usedonly after you have compiled a p

INPUT_REFERENCEAllows you to specify the VREF pin for the I/O standard being used by an I/O pin. This option is ignoredif it is applied to anything ot

INPUT_TERMINATIONAllows the Compiler to configure the on-chip termination (OCT) and impedance matching for an I/Opin. OCT helps to prevent signal refl

INSERT_ADDITIONAL_LOGIC_CELLAllows the Compiler to insert an additional logic cell after the output(s) of the logic function to which it isapplied, pr

INTERNAL_FLASH_UPDATE_MODESpecifies the configuration mode used with the configuration scheme for configuring the device.TypeEnumerationValues• Dual I

INTERNAL_SCRUBBINGSpecifies internal scrubbing usage for the selected device. If internal scrubbing is turned on, the devicecorrects single error or d

IO_12_LANE_INPUT_DATA_DELAY_CHAINSpecifies the propagation delay for IO_12_LANE Input Data Delay Chain. This is an advanced option thatshould be used

IO_12_LANE_INPUT_STROBE_DELAY_CHAINSpecifies the propagation delay for IO_12_LANE Input Strobe Delay Chain. This is an advanced optionthat should be u

IO_MAXIMUM_TOGGLE_RATESpecifies the toggle rate of this node. You can specify the desired frequency setting. This option is ignoredif it is applied to

CLKLOCKX1_INPUT_FREQCreates an internal ClockLock phase-locked loop (PLL) and specifies its frequency. Turning this optionon is equivalent to instanti

IO_PLACEMENT_OPTIMIZATIONSpecifies whether the Fitter optimizes the location of IOs that do not already have pin locations assignedto them. Performing

IO_STANDARDSpecifies the I/O standard of a pin. Different device families support different I/O standards, andrestrictions apply to placing pins with

LVDS_DIRECT_LOOPBACK_MODEEnable the LVDS Direct Loop Mode on a True Differential output pin. This assignment should only applyfrom an input pin to an

LVDS_RX_REGISTERDirects the Compiler to perform special placement and routing of the specified register for LVDS receiverinterfacesTypeEnumerationValu

M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCYAllows you to specify whether the M144K memory block read operations depend upon the read clock'sduty

MATCH_PLL_COMPENSATION_CLOCKAllows you to specify a PLL output clock feeding a clock network as a compensation target for a PLL inNORMAL or SOURCE_SYN

MAX10FPGA_CONFIGURATION_SCHEMEThe method used to load a design into the device. Only one configuration scheme is available: InternalConfiguration (use

MAX7000B_VCCIO_IOBANK1Specifies the default I/O Bank1 Voltage to be used for pins on the target device.TypeStringDevice SupportThis setting can be use

MAX7000B_VCCIO_IOBANK2Specifies the default I/O Bank2 Voltage to be used for pins on the target device.TypeStringDevice SupportThis setting can be use

MAX7000_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.TypeStringDevice SupportThis setting can be used

CYCLONEII_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,minimize logic u

MAX7000_ENABLE_JTAG_BST_SUPPORTEnables JTAG boundary-scan test (BST) support.TypeBooleanDevice SupportThis setting can be used in projects targeting a

MAX7000_INDIVIDUAL_TURBO_BITControls the speed vs. power usage trade-off for a macrocell. If the Turbo Bit is on, the macrocell's speedincreases;

MAX_CLOCKS_ALLOWEDSpecifies the maximum number of clocks of any type (e.g. global clock, regional clock) that can be used bythe design. A value of -1

MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATIONSpecifies the number of consecutive horizontal output or bidirectional pins considered in the current-dens

MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATIONSpecifies the number of consecutive vertical output or bidirectional pins considered in the current-de

MAX_CURRENT_FOR_ELECTROMIGRATIONSpecifies the maximum amount of DC current, in mA, allowed on horizontal output or bidirectional pinswhen the Fitter c

MAX_CURRENT_FOR_VIO_ELECTROMIGRATIONSpecifies the maximum amount of DC current, in mA, allowed on vertical output or bidirectional pinswhen the Fitter

MAX_GLOBAL_CLOCKS_ALLOWEDSpecifies the maximum number of global clocks that can be used by the design. A value of -1 means thatthe fitter can use all

MAX_PERIPHERY_CLOCKS_ALLOWEDSpecifies the maximum number of periphery clocks that can be used by the design. A value of -1 meansthat the fitter can us

MAX_REGIONAL_CLOCKS_ALLOWEDSpecifies the maximum number of regional clocks that can be used by the design. A value of -1 means thatthe fitter can use

CYCLONE_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,minimize logic usa

MEMORY_INTERFACE_DATA_PIN_GROUPSpecifies the group width (4, 9, 18, or 36), and associates a pin with another pin. Turning on this optionallows the Fi

MEM_INTERFACE_DELAY_CHAIN_CONFIGChanges Quartus II Fitter behavior regarding delay chain configurations on memory interface pins. Thisoption is ignore

MERCURY_CONFIGURATION_SCHEMEThe method used to load data into the device. Three configuration schemes are available: Passive ParallelAsynchronous (PPA

MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLSDecreases the propagation delay from an input or bidirectional pin to logic and embedded cells within th

MERCURY_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.TypeStringDevice SupportThis setting can be used

MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEARAllows merging of HSSI TX PLLs if their reset input are driven by registers that have the sameasynchro

MIGRATION_CONSTRAIN_CORE_RESOURCESLimits the compiler to using only those core resources which are also available in the target migrationdeviceTypeBoo

MIGRATION_DEVICESShows the selected migration devices for the target device.TypeStringDevice SupportThis setting can be used in projects targeting any

NCEO_OPEN_DRAINSpecify open drain on the nCEO pin should be enabled or notTypeBooleanDevice SupportThis setting can be used in projects targeting any

NDQS_LOCAL_CLOCK_DELAY_CHAINSet the propagation delay on the NDQS signal to the input register of the target pin. This is an advancedoption that shoul

DEVICE_FILTER_PACKAGEPackage filter for available devices.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device fam

NORMAL_LCELL_INSERTDirects the Fitter to enable or disable logic cell insertion when the logic cells are not part of a carry orcascade chain. When thi

OE_DELAY_CHAINSpecifies the propagation delay for Output Enable Delay Chain. This is an advanced option that should beused only after you have compile

OPTIMIZE_FOR_METASTABILITYThis setting improves the reliability of the design by increasing its Mean Time Between Failures (MTBF).When this setting is

OPTIMIZE_HOLD_TIMINGAllows the Fitter to optimize hold time by adding delay to the appropriate paths. The Optimize Timingoption must be turned on in o

OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMINGControls whether the fitter optimizes I/O pin timing by automatically packing registers into I/Os tominimize

OPTIMIZE_MULTI_CORNER_TIMINGControls whether the Fitter optimizes a design to meet timing requirements at all process corners andoperating conditions.

OPTIMIZE_POWER_DURING_FITTINGControls the power-driven compilation setting of the Fitter. This option determines how aggressively theFitter optimizes

OPTIMIZE_SSNControls the Simultaneous Switching Noise (SSN) optimization setting of the Fitter. This optiondetermines how aggressively the Fitter opti

OPTIMIZE_TIMINGControls whether the Fitter optimizes to meet the maximum delay timing requirements (for example,clock cycle time). By default, this op

OUTPUT_BUFFER_DELAYSpecifies the delay value (in ps) for the Programmable Output Buffer Delay. Turning on this featureshould improve the output duty c

DEVICE_FILTER_PIN_COUNTPin count filter for available devices.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device

OUTPUT_BUFFER_DELAY_CONTROLSets the Programmable Output Buffer Delay control. Turning on this feature should improve the outputduty cycle at the cost

OUTPUT_DELAY_CHAINSpecifies the propagation delay for Output Delay Chain. This is an advanced option that should be usedonly after you have compiled a

OUTPUT_ENABLE_DELAYSpecifies the propagation delay to the output enable pin from internal logic or the output enable registerimplemented in an I/O cel

OUTPUT_ENABLE_GROUPAssigns an output enable group number for the specified node. Turning on this option directs the Fitter toview the specified nodes

OUTPUT_ENABLE_REGISTER_DUPLICATIONDuplicates a register that feeds to the output enable port of an I/O cell. Turning on this option can helpmaximize t

OUTPUT_ENABLE_ROUTINGSpecifies whether an output enable signal in an I/O cell should be driven by the peripheral bus or thesingle-pin path. The Single

OUTPUT_PIN_LOADSpecifies the capacitive load, in picofarads (pF), on output pins for each I/O standard. Note: These settingsaffect FPGA pins only. To

OUTPUT_TERMINATIONAllows the Compiler to configure the on-chip termination (OCT) and impedance matching for an I/Opin. OCT helps to prevent signal ref

OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERSSpecifies whether you want the Fitter to use default electromigration values, or if you want to specifymax

PAD_TO_CORE_DELAYSpecifies the propagation delay from an input or bidirectional pin to logic and embedded cells within thedevice. This is an advanced

DEVICE_FILTER_SPEED_GRADESpeed grade filter for available devices.TypeStringDevice SupportThis setting can be used in projects targeting any Altera de

PAD_TO_DDIO_REGISTER_DELAYSpecifies the propagation delay from an input pin to the data input of the DDIO low capture inputregister in the I/O cell as

PAD_TO_INPUT_REGISTER_DELAYSpecifies the propagation delay from an input pin to the data input of the input register implemented inthe I/O cell associ

PCI_IOTurns on Peripheral Component Interconnect (PCI) compatibility for a pin. For example, when theVCCIO of an EP20K400 device operates at 3.3 V and

PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELININGSpecifies that Quartus II should perform automatic insertion of pipeline stages for asynchronous clea

PHYSICAL_SYNTHESIS_COMBO_LOGICSpecifies that Quartus should perform physical synthesis optimizations on combinational logic duringsynthesis and fittin

PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREASpecifies that the Fitter should perform physical synthesis optimizations on combinational logic duringfitting

PHYSICAL_SYNTHESIS_EFFORTSpecifies the amount of effort, in terms of compile time, physical synthesis should use. Compared to theDefault setting, a se

PHYSICAL_SYNTHESIS_LOG_FILESpecifies the log file that lists all the FSYN operations performed in a previous compile that need to bereproduced. This l

PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREASpecifies that the Fitter should perform physical synthesis optimizations on logic and registers, speci

PHYSICAL_SYNTHESIS_REGISTER_DUPLICATIONSpecifies that the Fitter should perform physical synthesis optimizations on registers, specifically allowingre

DEVICE_FILTER_VOLTAGEVoltage filter for available devices.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device fam

PHYSICAL_SYNTHESIS_REGISTER_RETIMINGSpecifies that Quartus should perform physical synthesis optimizations on registers, specifically allowingregister

PLACEMENT_EFFORT_MULTIPLIERControls how much time the fitter spends in placement. The default value is 1.0 and legal values must begreater than 0. Spe

PLL_AUTO_RESETCauses the PLL to self-reset automatically on loss of lock.TypeBooleanDevice SupportThis setting can be used in projects targeting any A

PLL_BANDWIDTH_PRESETSpecifies the PLL bandwidth preset setting.TypeEnumerationValues• Auto• High• Low• MediumDevice SupportThis setting can be used in

PLL_CHANNEL_SPACINGSpecifies the PLL channel spacing. The PLL channel spacing is the frequency difference betweensuccessive oscillations of the feedba

PLL_COMPENSATEAllows you to specify an output pin as a compensation target for a PLL in ZERO_DELAY_BUFFER orEXTERNAL_FEEDBACK mode, or an input pin or

PLL_COMPENSATION_MODESpecifies the routing path of the PLL feedback clock and adjusts the delay chains in the PLL.TypeEnumerationValues• Direct• Exter

PLL_ENFORCE_USER_PHASE_SHIFTEnsures that phase shift requirements are given higher priority.TypeBooleanDevice SupportThis setting can be used in proje

PLL_FEEDBACK_CLOCK_SIGNALAllows you to specify whether PLL feedback clock signal should be routed using global or regional routingpaths in the PLL con

PLL_FORCE_OUTPUT_COUNTERForces which counter to use for a particular PLL clock output. By default the compiler will automaticallydetermine the best co

DISABLE_DSP_NEGATE_INFERENCINGAllow you to specify whether to use the negate port on an inferred DSP block.TypeBooleanDevice SupportThis setting can b

PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAYForces which counter to use for a particular PLL clock output. By default the compiler will automaticallydeter

PLL_IGNORE_MIGRATION_DEVICESForces the compiler to ignore the migration devices when calculating the PLL settings. Normally the PLLis configured to wo

PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMINGAllows the Fitter to set the phase shift of a PLL output counter, and hence the phase shift of its generatedclock,

PLL_OUTPUT_CLOCK_FREQUENCYSpecifies the output clock frequency of the PLL.TypeFrequencyDevice SupportThis setting can be used in projects targeting an

PLL_PFD_CLOCK_FREQUENCYSpecifies the phase frequency detector (PFD) clock frequency.TypeFrequencyDevice SupportThis setting can be used in projects ta

PLL_TYPESpecifies a specific PLL implementation to target.TypeEnumerationValues• ATX• CMU• IOPLL• fPLLDevice SupportThis setting can be used in projec

PLL_VCO_CLOCK_FREQUENCYSpecifies the voltage controlled oscillator (VCO) output clock frequency.TypeFrequencyDevice SupportThis setting can be used in

PRESERVE_PLL_COUNTER_ORDERPreserves the order of PLL clock outputs used when selecting corresponding output counters. Forexample, a clk0 output will u

PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILESSets an upper limit on the fraction of the LAB tiles used by your design that can be h

PROGRAMMABLE_POWER_TECHNOLOGY_SETTINGControls how the fitter configures tiles to operate in high-speed mode or low-power mode. Automaticspecifies that

BOARD_MODEL_FAR_PULLUP_RSpecifies, in ohms, the board trace model far pull-up resistance.TypeStringDevice SupportThis setting can be used in projects

DISABLE_OCP_HW_EVALTurns off OpenCore Plus hardware evaluation feature.TypeBooleanDevice SupportThis setting can be used in projects targeting any Alt

PROGRAMMABLE_PREEMPHASISImplements control of programmable pre-emphasis, which helps compensate for high frequency losses.This option is ignored if it

PROGRAMMABLE_VODImplements control of programmable VOD. This option is ignored if it is applied to anything other thanan output or bidirectional pin,

PR_DONE_OPEN_DRAINSpecify open drain on the PR_DONE pin should be enabled or notTypeBooleanDevice SupportThis setting can be used in projects targetin

PR_ERROR_OPEN_DRAINSpecify open drain on the PR_ERROR pin should be enabled or notTypeBooleanDevice SupportThis setting can be used in projects target

PR_PINS_OPEN_DRAINSpecify open drain on the Partial Reconfiguration pins (PR_READY, PR_ERROR, and PR_DONE)should be enabled or notTypeBooleanDevice Su

PR_READY_OPEN_DRAINSpecify open drain on the PR_READY pin should be enabled or notTypeBooleanDevice SupportThis setting can be used in projects target

QDR_D_PIN_GROUPAssigns a quad data rate (QDR) D (data) output pin group number to a specified pin. Turning on thisoption allows the Fitter to view pin

QII_AUTO_PACKED_REGISTERSAllows the Compiler to combine a register and a combinational function, or to implement registers usingI/O cells, RAM blocks,

Syntax set_global_assignment -name QII_AUTO_PACKED_REGISTERS <value> set_global_assignment -name QII_AUTO_PACKED_REGISTERS -entity

RESERVE_ALL_UNUSED_PINSReserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs thatdrive ground, a

DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIESSpecifies whether registers that are in different hierarchies are allowed to be merged if their inputs are

RESERVE_ALL_UNUSED_PINS_WEAK_PULLUPReserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs thatdri

RESERVE_ASDO_AFTER_CONFIGURATIONSpecifies how the ASDO pin should be used when the device is operating in user mode after configurationis complete. De

RESERVE_DATA0_AFTER_CONFIGURATIONSpecifies how the Data[0] pin should be used when the device is operating in user mode afterconfiguration is complete

RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATIONSpecifies how the Data[15..8] pins should be used when the device is operating in user mode afterconfi

RESERVE_DATA1_AFTER_CONFIGURATIONSpecifies how the Data[1]/ASDO pin should be used when the device is operating in user mode afterconfiguration is com

RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATIONSpecifies how the Data[31..16] pins should be used when the device is operating in user mode aftercon

RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATIONSpecifies how the Data[7..1] pins should be used when the device is operating in user mode afterconfigu

RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATIONSpecifies how the Data[7..2] pins should be used when the device is operating in user mode afterconfigu

RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATIONSpecifies how the Data[7..5] pins should be used when the device is operating in user mode afterconfigu

RESERVE_DCLK_AFTER_CONFIGURATIONSpecifies how the DCLK pin should be used when the device is operating in user mode after configurationis complete. De

DONT_MERGE_REGISTERWhen set to On, this option prevents the specified register from merging with other registers, andprevents other registers from mer

RESERVE_FLASH_NCE_AFTER_CONFIGURATIONSpecifies how the FLASH_nCE/nCSO pin should be used when the device is operating in user mode afterconfiguration

RESERVE_FLEXIBLE_CLOCK_NETWORKAllows you to specify whether this clock should be routed using only flexible section clock networkrouting. This setting

RESERVE_NCEO_AFTER_CONFIGURATIONSpecifies how the nCEO pin should be used when the device is operating in user mode after configurationhas been comple

RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATIONSpecifies how the nWS, nRS, nCS, and CS pins should be used when the device is operating in user modeafter c

RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATIONSpecifies how the Data[15..8], PADD[23..0], NRESET, NAVD, NOE and NWE pins should be used whenthe device is o

RESERVE_RDYNBUSY_AFTER_CONFIGURATIONSpecifies how the RDYnBUSY pin should be used when the device is operating in user mode afterconfiguration is comp

ROUTER_CLOCKING_TOPOLOGY_ANALYSISDirects the router to perform an analysis of the design's clocking topology and adjust the optimizationapproach

ROUTER_EFFORT_MULTIPLIERControls how quickly the router tries to find a valid solution. The default value is 1.0 and legal values mustbe greater than

ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATIONAllows the Fitter to automatically insert buffer logic cells between two nodes without altering thefunctio

ROUTER_REGISTER_DUPLICATIONAllows the Fitter to automatically duplicate registers within a LAB containing empty logic cells. Thisoption does not alter

DQS_DELAYIncreases the propagation delay from a DQS I/O pin to the interior of the device. This option is used tocenter-align the DQS signal to the DQ

ROUTER_TIMING_OPTIMIZATION_LEVELControls how aggressively the router tries to meet timing requirements. Setting this option to Maximumcan increase des

ROW_GLOBAL_SIGNALSpecifies whether the signal should be available throughout the device on the global routing pathsavailable within each row. Row-glob

RZQ_GROUPSpecifies an RZQ pin name and an OCT to terminate the given pin. Using the same RZQ pin nameinstructs the fitter to use the same OCT to termi

SCE_PINSpecifies the SCE configuration pin.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThis

SDO_PINSpecifies the SDO configuration pin.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.NotesThis

SEEDSpecifies the starting value the Fitter uses when randomly determining the initial placement for thecurrent design. The value can be any non-negat

SLEW_RATEImplements control of low-to-high/high-to-low transitions on output pins to help reduce switching noise.When a large number of output pins sw

SLOW_SLEW_RATEImplements slow low-to-high/high-to-low transitions on output pins to help reduce switching noise.When a large number of output pins swi

STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESETAllows the compiler to enable netlist placements and routing where the dedicated reference clock pad in

STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODEEnables the double data width (channel widths of 16 and 20) GIGE mode operation of GXB Receiver andTrans

DQS_FREQUENCYSpecifies the DQS system clock frequency by which data is transferred between a device and an externalRAM that uses double data rate (DDR

STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGEEnables GIGE configurations of GXB Receiver and Transmitter channels to operate at other dataratesthan 1

STRATIXGX_ALLOW_GIGE_WITHOUT_8B10BEnables GIGE configurations of GXB Receiver and Transmitter channels where the 8B10B decoder andencoder are not used

STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHEREnables GIGE configurations of GXB Receiver channels with the coreclk selected at the rate m

STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCEAllows GIGE configurations of GXB Receiver channels where the coreclk input is fed from anot

STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODEEnables the double data width (channel widths of 16 and 20) parallel loopback mode operatio

STRATIXGX_ALLOW_POST8B10B_LOOPBACKAllows Post 8B10B parallel loopback configurations of GXB Receiver and Transmitter channelsTypeBooleanDevice Support

STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACKAllows Reverse parallel loopback configurations of GXB Receiver and Transmitter channelsTypeBooleanDevice Sup

STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODEEnables the GXB Receiver coreclk input to be sourced from a different si

STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOSDirects the compiler to allow the use of I/O pins that couple onto the GXB I/O banksTypeBooleanDevice SupportThi

STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODEEnables single data width (channel width of 8) XAUI mode operation of GXB Receiver and Transmitterchanne

DQS_SHIFTSpecifies the interval of arrival between the DQ data signals and DQS signal during data transfer betweena device and an external RAM that us

STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHEREnables XAUI configurations of GXB Receiver channels with the coreclk selected at the rate m

STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCEAllows XAUI configurations of GXB Receiver channels where the coreclk input is fed from anot

STRATIXGX_TERMINATION_VALUEAllows the Compiler to configure the on-chip termination (OCT) for a Stratix GX gigabit transceiverblock (GXB) receiver cha

STRATIXIIGX_TERMINATION_VALUEAllows the Compiler to configure the on-chip termination (OCT) for a Stratix II GX gigabit transceiverblock (GXB) receive

STRATIXIII_CONFIGURATION_SCHEMEThe method used to load data into the device. Three configuration schemes are available: Passive Serial(PS); Fast Passi

STRATIXIII_MRAM_COMPATIBILITYDirect Quartus II software to produce programming files that are compatible with all silicon revisions.Please see the Str

STRATIXIII_UPDATE_MODESpecifies the configuration mode used with the configuration scheme for configuring the device.TypeEnumerationValues• Remote• St

STRATIXII_CONFIGURATION_SCHEMEThe method used to load data into the device. Four configuration schemes are available: Passive ParallelAsynchronous (PP

STRATIXII_TERMINATIONAllows the Compiler to configure the on-chip termination (OCT) and impedance matching for an I/Opin. OCT helps to prevent signal

STRATIXV_CONFIGURATION_SCHEMEThe method used to configure a device with a design. Up to six configuration schemes are available:Passive Serial (PS), P

DQS_SYSTEM_CLOCKSpecifies the clock input used as a frequency reference for a DQS I/O pin. The clock is the pin that drivesthe DDIO circuitry for the

STRATIX_CONFIGURATION_SCHEMEThe method used to load data into the device. Three configuration schemes are available: Passive ParallelAsynchronous (PPA

STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLSDecreases the propagation delay from an input or bidirectional pin to logic and embedded cells within th

STRATIX_DEVICE_IO_STANDARDSpecifies the default I/O standard to be used for pins on the target device.Old NameYEAGER_DEVICE_IO_STANDARDTypeStringDevic

STRATIX_UPDATE_MODESpecifies the configuration mode used with the configuration scheme for configuring the device.Old NameYEAGER_UPDATE_MODETypeEnumer

SYNCHRONIZER_IDENTIFICATIONSpecifies how the TimeQuest Timing Analyzer identifies registers as being part of a synchronizationregister chain for metas

name> <value> set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION -to <to> -entity <entity name> <value> De

SYNCHRONIZER_TOGGLE_RATESpecifies the toggle rate of this register. The units for this value are in transitions per second, and must bepositive. This

T11_0_DELAYSpecifies the propagation delay for the gated T11 delay cell. Use this advanced option only after you havecompiled a project, checked the I

T11_1_DELAYSpecifies the propagation delay for the ungated T11 delay cell. Use this advanced option only after youhave compiled a project, checked the

T11_DELAYSpecifies the propagation delay for T11 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, che

DSE_SYNTH_EXTRA_EFFORT_MODESpecifies the Design Space Explorer synthesis extra effort mode.TypeEnumerationValues• MODE_1• MODE_2• MODE_3• MODE_4• MODE

T11_FINE_DELAYEnable the fine delay resolution on T11 Delay (DQS post-amble delay cell)TypeBooleanDevice SupportThis setting can be used in projects t

T4_DELAYSpecifies the propagation delay for T4 Delay Cell (Output register to switch mux). This is an advancedoption that should be used only after yo

T8_DELAY0Specifies the propagation delay for T8 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, chec

T8_DELAY1Specifies the propagation delay for T8 Delay Cell. This is an advanced option that should be used onlyafter you have compiled a project, chec

TERMINATIONAllows the Compiler to configure the on-chip termination (OCT) and impedance matching for an I/Opin. OCT helps to prevent signal reflection

TERMINATION_CONTROL_BLOCKSpecifies the control block used for calibrated on-chip termination (OCT) and impedance matching foran I/O pin. OCT helps to

TREAT_BIDIR_AS_OUTPUTDirects the bidirectional pin to be essentially treated as an output pin meaning that the input path is usedfor feedback from the

TRI_STATE_SPI_PINSThis option controls Active Configuration Controller to tri-state the Active Configuration pins in usermode. This option would be ig

TURBO_BITControls the speed vs. power usage trade-off for a macrocell (that is, for an embedded cell within anEmbedded System Block [ESB] that is set

TXPMA_SLEW_RATETo overwrite TX PMA slew rate to 4 options: Off, Low, Medium, High.TypeEnumerationValues• High• Low• Medium• OffDevice SupportThis sett

DSP_BLOCK_BALANCINGAllows you to control the conversion of certain DSP block slices during DSP block balancing.TypeEnumerationValues• Auto• DSP blocks

UNFORCE_MERGE_PLLPrevents the specified PLL to be merged with the master PLL. Use this option only for two compatiblePLLs driven by the same clock sou

UNFORCE_MERGE_PLL_OUTPUT_COUNTERPrevents the specified PLL output counter to be merged with the master PLL output counter. Use thisoption only for two

UNUSED_TSD_PINS_GNDIf this option is turned on, unused temperature sensing diode (TSD) pins, TEMPDIODEp/TEMPDIODEn, on the device are automatically se

USER_START_UP_CLOCKDirects the device to use a user-supplied clock on the CLKUSR pin for initialization.Old NameUser Specified Start-up clockTypeBoole

VCCIO_CURRENT_1PT8VFor user to override VCCIO current of 1.8-V io standard. Original current is 2mATypeIntegerDevice SupportThis setting can be used i

VCCIO_CURRENT_2PT5VFor user to override VCCIO current of 2.5-V io standard. Original current is 2mATypeIntegerDevice SupportThis setting can be used i

VCCIO_CURRENT_GTLFor user to override VCCIO current of GTL. Not yet supported in MAX7000.TypeIntegerDevice SupportThis setting can be used in projects

VCCIO_CURRENT_GTL_PLUSFor user to override VCCIO current of GTL+. Original current is 0mATypeIntegerDevice SupportThis setting can be used in projects

VCCIO_CURRENT_LVCMOSFor user to override VCCIO current of LVCMOS. Original current is 2mATypeIntegerDevice SupportThis setting can be used in projects

VCCIO_CURRENT_LVTTLFor user to override VCCIO current of LVTTL. Original current is 4mATypeIntegerDevice SupportThis setting can be used in projects t

EDA_DESIGN_ENTRY_SYNTHESIS_TOOLSpecifies the third-party EDA tool used for design entry/synthesisTypeStringDevice SupportThis setting can be used in p

VCCIO_CURRENT_PCIFor user to override VCCIO current of PCI. Original current is 4mATypeIntegerDevice SupportThis setting can be used in projects targe

VCCIO_CURRENT_SSTL2_CLASS1For user to override VCCIO current of SSTL2_CLASS1. Original current is 14mATypeIntegerDevice SupportThis setting can be use

VCCIO_CURRENT_SSTL2_CLASS2For user to override VCCIO current of SSTL2_CLASS2. Original current is 21mATypeIntegerDevice SupportThis setting can be use

VCCIO_CURRENT_SSTL3_CLASS1For user to override VCCIO current of SSTL3_CLASS1. Original current is 18mATypeIntegerDevice SupportThis setting can be use

VCCIO_CURRENT_SSTL3_CLASS2For user to override VCCIO current of SSTL3_CLASS2. Original current is 25mATypeIntegerDevice SupportThis setting can be use

VCCPD_VOLTAGESpecifies the default I/O Bank VCCPD Voltage to be used for pins on the target device.TypeStringDevice SupportThis setting can be used in

VREF_MODESpecifies VREF mode of a pin.TypeEnumerationValues• CALIBRATED• EXTERNAL• VCCIO_45• VCCIO_50• VCCIO_55• VCCIO_65• VCCIO_70• VCCIO_75Device Su

WEAK_PULL_UP_RESISTOREnables the weak pull-up resistor when the device is operating in user mode. This option pulls a high-impedance bus signal to VCC

XCVR_A10_REFCLK_TERM_TRISTATEA logic option that directs the Compiler to enable the internal termination of the dedicated referenceclock pin.TypeEnume

XCVR_A10_RX_ADP_CTLE_ACGAIN_4SA logic option that allows you to control the amount of AC gain on the equalizer in high gain mode. Theamount of AC gain

BOARD_MODEL_FAR_SERIES_RSpecifies, in ohms, the board trace model far series resistance.TypeStringDevice SupportThis setting can be used in projects t

EDA_INPUT_DATA_FORMATSpecifies the format of the input data read from other EDA design entry/synthesis tools.TypeStringDevice SupportThis setting can

NotesSyntax set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S -to <to> -entity <entity name> <value> 800XCVR_A1

XCVR_A10_RX_ADP_CTLE_EQZ_1S_SELA logic option that allows you to control the amount of AC gain on the one-stage equalizer. The amountof AC gain is pro

XCVR_A10_RX_ADP_DFE_FXTAP1A logic option that allows you to specify the coefficient setting for fix tap one in the receiver decisionfeedback equalizer

• RADP_DFE_FXTAP1_18• RADP_DFE_FXTAP1_19• RADP_DFE_FXTAP1_2• RADP_DFE_FXTAP1_20• RADP_DFE_FXTAP1_21• RADP_DFE_FXTAP1_22• RADP_DFE_FXTAP1_23• RADP_DFE_

• RADP_DFE_FXTAP1_61• RADP_DFE_FXTAP1_62• RADP_DFE_FXTAP1_63• RADP_DFE_FXTAP1_64• RADP_DFE_FXTAP1_65• RADP_DFE_FXTAP1_66• RADP_DFE_FXTAP1_67• RADP_DFE

NotesSyntax set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 -to <to> -entity <entity name> <value> MNL-Q210052015

XCVR_A10_RX_ADP_DFE_FXTAP2A logic option that allows you to specify the coefficient setting for fix tap two in the receiver decisionfeedback equalizer

• RADP_DFE_FXTAP2_18• RADP_DFE_FXTAP2_19• RADP_DFE_FXTAP2_2• RADP_DFE_FXTAP2_20• RADP_DFE_FXTAP2_21• RADP_DFE_FXTAP2_22• RADP_DFE_FXTAP2_23• RADP_DFE_

• RADP_DFE_FXTAP2_61• RADP_DFE_FXTAP2_62• RADP_DFE_FXTAP2_63• RADP_DFE_FXTAP2_64• RADP_DFE_FXTAP2_65• RADP_DFE_FXTAP2_66• RADP_DFE_FXTAP2_67• RADP_DFE

NotesSyntax set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 -to <to> -entity <entity name> <value> MNL-Q210052015

EDA_INPUT_GND_NAMESpecifies the global high signal used in the files generated by the EDA synthesis tool, which is GND.TypeStringDevice SupportThis se

XCVR_A10_RX_ADP_DFE_FXTAP3A logic option that allows you to specify the coefficient setting for fix tap three in the receiver decisionfeedback equaliz

• RADP_DFE_FXTAP3_18• RADP_DFE_FXTAP3_19• RADP_DFE_FXTAP3_2• RADP_DFE_FXTAP3_20• RADP_DFE_FXTAP3_21• RADP_DFE_FXTAP3_22• RADP_DFE_FXTAP3_23• RADP_DFE_

• RADP_DFE_FXTAP3_61• RADP_DFE_FXTAP3_62• RADP_DFE_FXTAP3_63• RADP_DFE_FXTAP3_64• RADP_DFE_FXTAP3_65• RADP_DFE_FXTAP3_66• RADP_DFE_FXTAP3_67• RADP_DFE

NotesSyntax set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 -to <to> -entity <entity name> <value> MNL-Q210052015

XCVR_A10_RX_ADP_DFE_FXTAP4A logic option that allows you to specify the coefficient setting for floating tap four in the receiver decisionfeedback equ

• RADP_DFE_FXTAP4_43• RADP_DFE_FXTAP4_44• RADP_DFE_FXTAP4_45• RADP_DFE_FXTAP4_46• RADP_DFE_FXTAP4_47• RADP_DFE_FXTAP4_48• RADP_DFE_FXTAP4_49• RADP_DFE

XCVR_A10_RX_ADP_DFE_FXTAP5A logic option that allows you to specify the coefficient setting for fix tap five in the receiver decisionfeedback equalize

• RADP_DFE_FXTAP5_43• RADP_DFE_FXTAP5_44• RADP_DFE_FXTAP5_45• RADP_DFE_FXTAP5_46• RADP_DFE_FXTAP5_47• RADP_DFE_FXTAP5_48• RADP_DFE_FXTAP5_49• RADP_DFE

XCVR_A10_RX_ADP_DFE_FXTAP6A logic option that allows you to specify the coefficient setting for fix tap six in the receiver decisionfeedback equalizer

NotesSyntax set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 -to <to> -entity <entity name> <value> MNL-Q210052015

EDA_INPUT_VCC_NAMESpecifies the global power-down signal.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device fami

XCVR_A10_RX_ADP_DFE_FXTAP7A logic option that allows you to specify the coefficient setting for fix tap seven in the receiver decisionfeedback equaliz

NotesSyntax set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 -to <to> -entity <entity name> <value> MNL-Q210052015

XCVR_A10_RX_ADP_VGA_SELA logic option that allows you to controls the amount of output voltage swing on the variable gainamplifier. The amount of volt

XCVR_A10_RX_EQ_DC_GAIN_TRIMA logic option that allows you to control the amount of DC gain on equalizer in high gain mode. Theamount of DC gain is pro

NotesSyntax set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM -to <to> -entity <entity name> <value> 824XCVR_A10_R

XCVR_A10_RX_LINKA logic option that allows you to specify the type of communication for the receiver link. Quartus II willuse this option to determine

XCVR_A10_RX_ONE_STAGE_ENABLETypeEnumerationValues• NON_S1_MODE• S1_MODEDevice SupportThis setting can be used in projects targeting any Altera device

XCVR_A10_RX_TERM_SELA logic option that allows you to specify the termination value of the receiver pin.TypeEnumerationValues• R_EXT0• R_R1• R_R2Devic

XCVR_A10_TX_COMPENSATION_ENA logic option that allows you to turn on the compensation for transmitter data rate above 9 Gbps.Turning on this option dr

XCVR_A10_TX_LINKA logic option that allows you to specify the type of communication for the transmitter link. Quartus IIwill use this option to determ

EDA_LMF_FILESpecifies the default Library Mapping File (.lmf) for the current compilation.TypeFile nameDevice SupportThis setting can be used in proje

XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAPA logic option that allows you to specify the output polarity of the transmitter pre-emphasis first post-tap.Type

XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAPA logic option that allows you to specify the output polarity of the transmitter pre-emphasis second post-tap.Typ

XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1TA logic option that allows you to specify the output polarity of the transmitter pre-emphasis first pre-tap.TypeEnu

XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2TA logic option that allows you to specify the output polarity of the transmitter pre-emphasis second pre-tap.TypeEn

XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAPA logic option that allows you to control the magnitude of transmitter pre-emphasis first post-tap. Leg

XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAPA logic option that allows you to control the magnitude of transmitter pre-emphasis second post-tap.Leg

XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1TA logic option that allows you to control the magnitude of transmitter pre-emphasis first pre-tap. Legalv

XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2TA logic option that allows you to control the magnitude of transmitter pre-emphasis second pre-tap. Legal

XCVR_A10_TX_VOD_OUTPUT_SWING_CTRLA logic option that allows you to control the transmitter output swing level. Legal values are: 0 to 31.TypeIntegerDe

XCVR_ANALOG_SETTINGS_PROTOCOLSpecify protocol and its variant that are used to determine electrical analog settings for the transceiver.Old NameHSSI_A

EDA_RUN_TOOL_AUTOMATICALLYRuns the third-party EDA tool automatically from Quartus II when a design is compiled.TypeBooleanDevice SupportThis setting

• OBSAI_768• PCIE_CABLE• PCIE_GEN1• PCIE_GEN1_3P5DB• PCIE_GEN2• PCIE_GEN2_3P5DB• PCIE_GEN2_6DB• PCIE_GEN3• QPI• QSGMII_5000• SATA1_I• SATA1_M• SATA1_X

NotesThis assignment supports Fitter wildcards.Syntax set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL -to <to> -entity <en

XCVR_GT_IO_PIN_TERMINATIONAllows the Compiler to configure the GT transceiver termination value.TypeIntegerDevice SupportThis setting can be used in p

XCVR_GT_RX_COMMON_MODE_VOLTAGEGT receiver buffer common-mode voltage.TypeEnumerationValues• VTT_0P35V• VTT_0P50V• VTT_0P55V• VTT_0P60V• VTT_0P65V• VTT

XCVR_GT_RX_CTLEStatic control for the continuous time equalizer in the receiver buffer.TypeIntegerDevice SupportThis setting can be used in projects t

XCVR_GT_RX_DC_GAINControls the amount of a stage receive-buffer DC gain.TypeIntegerDevice SupportThis setting can be used in projects targeting any Al

XCVR_GT_TX_COMMON_MODE_VOLTAGEGT Transmitter common-mode driver voltageTypeEnumerationValues• GROUNDED• PULL_DN• PULL_UP• PULL_UP_TO_VCCELA• TRISTATED

XCVR_GT_TX_PRE_EMP_1ST_POST_TAPSpecifies the GT transmitter preemphasis first post-tap setting value.TypeIntegerDevice SupportThis setting can be used

XCVR_GT_TX_PRE_EMP_INV_PRE_TAPInverts the GT transmitter preemphasis pre-tap setting value.TypeBooleanDevice SupportThis setting can be used in projec

XCVR_GT_TX_PRE_EMP_PRE_TAPSpecifies the GT transmitter preemphasis pre-tap setting value.TypeIntegerDevice SupportThis setting can be used in projects

EDA_SHOW_LMF_MAPPING_MESSAGESDetermines whether to display messages describing the mappings used in the Library Mapping File.TypeBooleanDevice Support

XCVR_GT_TX_VOD_MAIN_TAPDifferential output voltage setting for GT.TypeIntegerDevice SupportThis setting can be used in projects targeting any Altera d

XCVR_IO_PIN_TERMINATIONAllows the Compiler to configure the Transceiver Termination value for a GXB I/O pin. It specifies theintended Transceiver Term

XCVR_RECONFIG_GROUPAssigns the node you specify to a transceiver Avalon Memory-Mapped interface group. The AvalonMemory-Mapped interfaces of an RX-onl

XCVR_REFCLK_PIN_TERMINATIONAllows the Compiler to configure the Termination value for a dedicated refclk pin. It specifies theintended Termination val

XCVR_RX_ACGAIN_ASets reference voltage on EQATypeEnumerationValues• AREF_VOLT_0• AREF_VOLT_0P5• AREF_VOLT_0P75• AREF_VOLT_1P0Device SupportThis settin

XCVR_RX_ACGAIN_VSets reference voltage on EQVTypeEnumerationValues• VREF_VOLT_0• VREF_VOLT_0P5• VREF_VOLT_0P75• VREF_VOLT_1P0Device SupportThis settin

XCVR_RX_BYPASS_EQ_STAGES_234Bypasses continuous time equalizer stages 2, 3, and 4 to save power. This assignment eliminatessignificant AC gain on the

XCVR_RX_COMMON_MODE_VOLTAGEReceiver buffer common-mode voltage.TypeEnumerationValues• TRISTATE1• VTT_0P35V• VTT_0P50V• VTT_0P55V• VTT_0P60V• VTT_0P65V

XCVR_RX_DC_GAINControls the amount of a stage receive-buffer DC gain.TypeIntegerDevice SupportThis setting can be used in projects targeting any Alter

XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODEIf enabled, equalizer gain control is driven by the PCS block for PCI Express. If disabled, equalizer gaincont

EDA_VHDL_LIBRARYSpecifies the logical name of a user-defined VHDL design library : physical name.TypeStringDevice SupportThis setting can be used in p

XCVR_RX_EQ_BW_SELSets the gain peaking frequency for the equalizer. For data-rates of less than 6.5Gbps, set to HALF. Forhigher data-rates, set to FUL

XCVR_RX_INPUT_VCM_SELWhen set to LOW_VCM, this assignment enables PMOS equalizer on stage 1 of the input buffer anddisables the NMOS stage for QPI and

XCVR_RX_LINEAR_EQUALIZER_CONTROLStatic control for the continuous time equalizer in the receiver buffer. The equalizer has 16 distinctsettings from 0

XCVR_RX_SD_ENABLEEnables or disables the receiver signal detection unit.TypeBooleanDevice SupportThis setting can be used in projects targeting any Al

XCVR_RX_SD_OFFNumber of parallel cycles to wait before the signal detect block declares loss of signal.TypeIntegerDevice SupportThis setting can be us

XCVR_RX_SD_ONNumber of parallel cycles to wait before the signal detect block declares presence of signal.TypeIntegerDevice SupportThis setting can be

XCVR_RX_SD_THRESHOLDSpecifies signal detection voltage threshold level.TypeIntegerDevice SupportThis setting can be used in projects targeting any Alt

XCVR_RX_SEL_HALF_BWEnable half bandwidth mode. For BW=3.25GHZ, select FULL_BW. For BW=1.5GHz, select HALF_BWTypeEnumerationValues• FULL_BW• HALF_BWDev

XCVR_TX_COMMON_MODE_VOLTAGETransmitter common-mode driver voltageTypeEnumerationValuesVOLT_0P65VDevice SupportThis setting can be used in projects tar

XCVR_TX_PLL_RECONFIG_GROUPSpecifies whether XCVR channels with Dynamic TX PLL Reconfiguration can be merged.TypeIntegerDevice SupportThis setting can

ENABLE_IP_DEBUGMake certain nodes (for example, important registers, pins, and state machines) visible for all theMegaCore functions in a design. You

XCVR_TX_PRE_EMP_1ST_POST_TAPSpecifies the transmitter preemphasis first post-tap setting value.TypeIntegerDevice SupportThis setting can be used in pr

XCVR_TX_PRE_EMP_2ND_POST_TAPSpecifies the transmitter preemphasis second post-tap setting value.TypeIntegerDevice SupportThis setting can be used in p

XCVR_TX_PRE_EMP_2ND_POST_TAP_USERSpecifies the transmitter preemphasis second post-tap setting value, including inversion.TypeIntegerDevice SupportThi

XCVR_TX_PRE_EMP_INV_2ND_TAPInverts the transmitter preemphasis second post-tap setting value.TypeBooleanDevice SupportThis setting can be used in proj

XCVR_TX_PRE_EMP_INV_PRE_TAPInverts the transmitter preemphasis pre-tap setting value.TypeBooleanDevice SupportThis setting can be used in projects tar

XCVR_TX_PRE_EMP_PRE_TAPSpecifies the transmitter preemphasis pre-tap setting value.TypeIntegerDevice SupportThis setting can be used in projects targe

XCVR_TX_PRE_EMP_PRE_TAP_USERSpecifies the transmitter preemphasis pre-tap setting value, including inversion.TypeIntegerDevice SupportThis setting can

XCVR_TX_RX_DET_ENABLEEnables or disables the receiver detector circuit at the transmitter.TypeBooleanDevice SupportThis setting can be used in project

XCVR_TX_RX_DET_MODESets the mode for the receiver detect block function.TypeIntegerDevice SupportThis setting can be used in projects targeting any Al

XCVR_TX_RX_DET_OUTPUT_SELDetermines QPI or PCI Express mode for the Receiver Detect block.TypeEnumerationValues• RX_DET_PCIE_OUT• RX_DET_QPI_OUTDevice

ENABLE_M512Enables the compiler to use M512 memory blocks in a design. Because HardCopy II designs do notsupport M512 memory blocks, this option is us

XCVR_TX_SLEW_RATE_CTRLSpecifies the slew rate of the output signal. The valid values span from the slowest rate to fastest rate.TypeIntegerDevice Supp

XCVR_TX_VCM_CTRL_SRCControls the VCM driver (pulldown/pullup) dynamically from user signals when you set this assignmentto DYNAMIC_CTL for QPI protoco

XCVR_TX_VODDifferential output voltage setting. The values are monotonically increasing with the driver main tapcurrent strength.TypeIntegerDevice Sup

XCVR_TX_VOD_PRE_EMP_CTRL_SRCWhen you set this assignment to DYNAMIC_CTL for PCI Express, the PCS block controls the VOD andpreemphasis coefficients. W

XCVR_VCCA_VOLTAGEConfigure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage fora GXB I/O pin. If you do not set this

XCVR_VCCR_VCCT_VOLTAGEConfigure the VCCR_GXB and VCCT_GXB voltage for an GXB I/O pin by specifying the intendedsupply voltages for a GXB I/O pin. If t

XSTL_INPUT_ALLOW_SE_BUFFERAllows the pin with a Differential-XSTL IO-standard to be used with a single-ended input buffer.TypeBooleanDevice SupportThi

Incremental Compilation AssignmentsABSORB_PATHS_FROM_OUTPUTS_TO_INPUTSAllows the Compiler to optimize connections from a partition's outputs to i

ALLOW_MULTIPLE_PERSONASSpecifies if this partition represents a reconfigurable part of the design that can have mulitple personas(implementations)Type

AUTO_EXPORT_INCREMENTAL_COMPILATIONAutomatically exports the project as a design partitionTypeBooleanDevice SupportThis setting can be used in project

EXTRACT_VERILOG_STATE_MACHINESAllows the Compiler to extract state machines from Verilog Design Files. The Compiler optimizes statemachines using spec

CROSS_BOUNDARY_OPTIMIZATIONSThis setting specifies whether the Compiler should optimize across the partition's boundary. If enabled,the Compiler

ENABLE_LAB_SHARING_WITH_PARENT_PARTITIONAllows logic from the target partition to share LAB resources with the immediate parent partition.TypeBooleanD

ENABLE_STRICT_PRESERVATIONSpecifies whether IO pin belong to a strictly preserved safety IP. Setting defaults to off.TypeBooleanDevice SupportThis set

EXTENDS_TOP_BLOCKSpecifies a top-level block to extend. This currently instructs the fitter to use the post-map compilerresults from the given VLNV, a

IGNORE_PARTITIONSSpecifies whether the compiler should ignore partition assignments in the project.TypeBooleanDevice SupportThis setting can be used i

IMPORT_BLOCKSpecifies a block in the form of VLNV+Snapshot to be imported for the specified partition.TypeStringDevice SupportThis setting can be used

INCREMENTAL_COMPILATION_EXPORT_FILESpecifies the path to the exported file. The file must have a QXP file extensionTypeFile nameDevice SupportThis set

INCREMENTAL_COMPILATION_EXPORT_FLATTENSpecifies whether the netlist exported to the QXP file should flatten sub-partitionsTypeBooleanDevice SupportThi

INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAMESpecifies the name of the partition that contains the design hierarchy to be exported. The root partition

INCREMENTAL_COMPILATION_EXPORT_POST_FITSpecifies whether the exported QXP file contains the post-fit netlistTypeBooleanDevice SupportThis setting can

BOARD_MODEL_NEAR_CSpecifies, in farads, the board trace model near capacitance.TypeStringDevice SupportThis setting can be used in projects targeting

EXTRACT_VHDL_STATE_MACHINESAllows the Compiler to extract state machines from VHDL Design Files. The Compiler optimizes statemachines using special te

INCREMENTAL_COMPILATION_EXPORT_POST_SYNTHSpecifies whether the exported QXP file contains the post-synthesis netlistTypeBooleanDevice SupportThis sett

INCREMENTAL_COMPILATION_EXPORT_ROUTINGSpecifies whether the post-fit netlist exported to the QXP file contains routing informationTypeBooleanDevice Su

INPUT_PERSONASpecifies the input Persona file to use for this partition.TypeFile nameDevice SupportThis setting can be used in projects targeting any

INSERT_BOUNDARY_WIRE_LUTSEnables wire lut insertion for boundary ports in the given partition (the partition is named by hierarchypath). This ensures

MERGE_EQUIVALENT_BIDIRSAllows the Compiler to merge electrically equivalent bidirectional inputs. You must also enable the cross-boundary optimization

MERGE_EQUIVALENT_INPUTSAllows the Compiler to merge inputs connected to the same source. You must also enable the cross-boundary optimizations feature

PARTIAL_RECONFIGURATION_PARTITIONSpecifies if this partition in the design is partially reconfigurable.Old NamePR_PARTITIONTypeBooleanDevice SupportTh

PARTITION_ALWAYS_USE_QXP_NETLISTSpecifies whether to always use the netlist in the QXP file associated with the partition, either because theQXP file

PARTITION_ASD_REGION_IDIndicates the advanced sensitivity detection region assignment for this partition.TypeIntegerDevice SupportThis setting can be

PARTITION_ENABLE_STRICT_PRESERVATIONSpecifies whether partition is a strictly preserved safety IP. Setting defaults to off.TypeBooleanDevice SupportTh

FAMILYSpecifies the device family to use for compilation.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device fami

PARTITION_FITTER_PRESERVATION_LEVELSpecifies the amount of data to reuse when you specify to reuse the post-fit netlist of this partitionTypeEnumerati

PARTITION_HIERARCHYThe target of the assignment specifies the hierarchy path of the entity instance for the partition. The valueof the assignment spec

PARTITION_IGNORE_SOURCE_FILE_CHANGESSpecifies whether to use the requested post-synthesis or post-fit netlist when it is available, even whensource fi

PARTITION_IMPORT_ASSIGNMENTSSpecifies whether assignments (LogicLock or non-LogicLock) should be imported. If set to FALSE, onlythe netlist will be im

PARTITION_IMPORT_EXISTING_ASSIGNMENTSSpecifies the way existing and conflicting non-LogicLock region assignments should be handled duringimportTypeEnu

PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONSSpecifies the way existing and conflicting LogicLock region assignments should be handled during importType

PARTITION_IMPORT_FILESpecifies the name of the file from which to import the contents for the partition. This setting is only usedduring importation.T

PARTITION_IMPORT_PROMOTE_ASSIGNMENTSSpecifies whether assignments should be promoted to all instances of the imported entityTypeBooleanDevice SupportT

PARTITION_LAST_IMPORTED_FILESpecifies the name of the file from which the partition was last imported. This assignment is for purelyinformational purp

PARTITION_NETLIST_TYPESpecifies the type of netlist to use for this partition during the next compilationTypeEnumerationValues• Auto• EMPTY• IMPORTED•

FLEX10K_CARRY_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of both user-entered and Compiler-synthesizedCARRY_SUM buffers. Carry chai

PARTITION_PRESERVE_HIGH_SPEED_TILESSpecifies whether to preserve the high-speed tiles in the post-fit netlist, if applicable.TypeBooleanDevice Support

PROPAGATE_CONSTANTS_ON_INPUTSAllows the Compiler to use constants on a partition input to optimize the logic in the partition. You mustalso enable the

PROPAGATE_INVERSIONS_ON_INPUTSSpecifies that the Compiler should push inversions into partition inputs when possible. This cross-boundary optimization

QDB_FILESpecifies a QDB file to be imported to the current project.TypeStringDevice SupportThis setting can be used in projects targeting any Altera d

QDB_PATHSpecify path to read and write compiler generated database to a directory other than project directory.TypeStringDevice SupportThis setting ca

QHD_MODEEnables QHD Mode.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Syntax set_global_ass

RAPID_RECOMPILE_ASSIGNMENT_CHECKINGSpecifies whether to check if assignments have changed when running Rapid Recompile. Turning off thisoption will by

REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTSAllows the Compiler to remove logic connected to dangling partitions outputs. You must also enable thecross-boundar

LogicLock Region AssignmentsLL_AUTO_SIZESpecifies whether the LogicLock region is auto-sized. The Compiler determines an appropriate size forauto-size

LL_CORE_ONLYIf set to ON, the setting allows non-core tiles in the region.TypeBooleanDevice SupportThis setting can be used in projects targeting any

FLEX10K_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance orminimize logic u

LL_ENABLEDSpecifies whether the region is enabled.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera device family.Not

LL_HEIGHTSpecifies the height of the LogicLock region in rows.TypeIntegerDevice SupportThis setting can be used in projects targeting any Altera devic

LL_MEMBER_EXCEPTIONSIf specified, the Fitter assigns all nodes under the target design entity or path to be members of theLogicLock region, except for

LL_MEMBER_OFAssigns the current node(s) to a LogicLock region.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device

LL_MEMBER_OF_SECURITY_ROUTING_INTERFACEAssigns the current signal to a security routing interface.TypeStringDevice SupportThis setting can be used in

LL_ORIGINSpecifies the location of the LogicLock region's origin. For APEX 20K and APEX II devices, the origin isthe top left corner of the regio

LL_PARENTSpecifies the name of the LogicLock region's parent LogicLock region.TypeStringDevice SupportThis setting can be used in projects target

LL_PRIORITYIndicates the priority of a wildcard or path-based LL_MEMBER_OF assignment relative to other wildcardor path-based LL_MEMBER_OF assignments

LL_RESERVEDIf set to ON, the setting prevents the Fitter from placing non-member logic in the region.Old NameLL_RESERVETypeBooleanDevice SupportThis s

LL_ROOT_REGIONIndicates that the LogicLock region is a root region.TypeBooleanDevice SupportThis setting can be used in projects targeting any Altera

FLEX6K_CARRY_CHAIN_LENGTHSpecifies the maximum allowable length of a chain of both user-entered and Compiler-synthesizedCARRY_SUM buffers. Carry chain

LL_STATESpecifies whether the location of the LogicLock region is locked or floating. The Compiler determines anappropriate location for floating regi

LL_WIDTHSpecifies the width of the LogicLock region in LABs/ESBs.TypeIntegerDevice SupportThis setting can be used in projects targeting any Altera de

Migration AssignmentsMIGRATION_AUTO_PACKED_REGISTERSRegister Packings that have been performed on a prototype device and that must be reproduced on th

MIGRATION_AUTO_PORT_SWAPPort Swappings that have been performed on a prototype device and that must be reproduced on thetarget migration deviceTypeStr

MIGRATION_RAM_INFORMATIONRAMs that have been created on a prototype device and that must be reproduced on the target migrationdeviceTypeStringDevice S

Netlist Viewer AssignmentsRTLV_GROUP_COMB_LOGIC_IN_CLOUDAllow RTL Viewer to group combinational logic in logic cloudTypeBooleanDevice SupportThis sett

RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMVAllow Technology Map Viewer to group combinational logic in logic cloudTypeBooleanDevice SupportThis setting can be

RTLV_GROUP_RELATED_NODESAllow RTL Viewer to group all related nodes into a single bus nodeTypeBooleanDevice SupportThis setting can be used in project

RTLV_GROUP_RELATED_NODES_TMVAllow Technology Map Viewer to group all related nodes into a single bus nodeTypeBooleanDevice SupportThis setting can be

RTLV_REMOVE_FANOUT_FREE_REGISTERSAllow RTL Viewer to remove fanout free registersTypeBooleanDevice SupportThis setting can be used in projects targeti

FLEX6K_OPTIMIZATION_TECHNIQUESpecifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance orminimize logic us

RTLV_SIMPLIFIED_LOGICAllow RTL Viewer to remove wire nodes and merge chain of equivalent combinatorial gatesTypeBooleanDevice SupportThis setting can

Pin & Location AssignmentsAPEX20K_CLIQUE_TYPESpecifies the type of a clique.Old NameCLIQUE_TYPETypeEnumerationValuesLABDevice SupportThis setting

APEX20K_LOCAL_ROUTING_SOURCESpecifies that the fan-out(s) of an input pin connected to logic elements, or the fan-out(s) of a logicelement connected t

FAST_INPUT_REGISTERImplements an input register in a cell that has a fast, direct connection from an I/O pin. If such a fast,direct connection from th

FAST_OCT_REGISTERImplements an OCT register in a cell that has a fast, direct connection to an I/O pin. Turning on the FastOCT Register option can hel

FAST_OUTPUT_ENABLE_REGISTERImplements an output enable register in a cell that has a fast, direct connection to an I/O pin. If such afast, direct conn

FAST_OUTPUT_REGISTERImplements an output register in a cell that has a fast, direct connection to an I/O pin. If such a fast, directconnection to the

FLEX10K_CLIQUE_TYPESpecifies the type of a clique.TypeEnumerationValuesLABDevice SupportThis setting can be used in projects targeting any Altera devi

FLEX6K_CLIQUE_TYPESpecifies the type of a clique.TypeEnumerationValues• Best• Half Row• LAB• RowDevice SupportThis setting can be used in projects tar

FLEX6K_LOCAL_ROUTING_SOURCESpecifies that the fan-out(s) of an input pin connected to logic elements, or the fan-out(s) of a logicelement connected to

FORCE_SYNCH_CLEARForces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on thisoption helps to reduce the total

IP_DEBUG_VISIBLEWhen assigned to an Encrypted IP node this option directs Quartus II to display the node in the NodeFinder.TypeBooleanDevice SupportTh

LL_IGNORE_IO_PIN_SECURITY_CONSTRAINTAllows the specified I/O pin to ignore security constraints.TypeBooleanDevice SupportThis setting can be used in p

LOCATIONAssigns a location on the device for the current node(s) and/or pin(s).TypeLocationDevice SupportThis setting can be used in projects targetin

MAX7K_CLIQUE_TYPESpecifies the type of a clique.TypeEnumerationValuesLABDevice SupportThis setting can be used in projects targeting any Altera device

MEMBER_OFAssigns one or more currently selected nodes and/or entities to a clique, which is a group of functions thatthe Compiler attempts to place to

MERCURY_CLIQUE_TYPESpecifies the type of a clique.TypeEnumerationValuesLABDevice SupportThis setting can be used in projects targeting any Altera devi

PIN_CONNECT_FROM_NODEDirects the Compiler to generate a device pin with the specified name and connect the device pin to aninternal signal.TypeStringD

RESERVE_PINReserves the pin in one of seven states: as an input that is tri-stated; as an output that drives ground; as anoutput that drives VCC; as a

SUBCLIQUE_OFSpecifies that the current clique is a member of another clique.TypeStringDevice SupportThis setting can be used in projects targeting any

VIRTUAL_PINSpecifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logicelement and not to a pin during compila

HDL_INITIAL_FANOUT_LIMITDirects Integrated Synthesis to check the initial fan-out of each net in the netlist immediately afterelaboration but prior to

Power Estimation AssignmentsENABLE_SMART_VOLTAGE_IDSpecifies whether smart voltage ID feature is used.TypeBooleanDevice SupportThis setting can be use

POWER_AUTO_COMPUTE_TJSpecifies whether the junction temperature is auto-computed during power estimation. If the junctiontemperature is not auto-compu

POWER_BOARD_TEMPERATURESpecifies the board temperature, in degrees Celsius, used during power estimation.TypeIntegerDevice SupportThis setting can be

POWER_BOARD_THERMAL_MODELSpecifies the board thermal model used during power estimation.TypeStringDevice SupportThis setting can be used in projects t

POWER_DEFAULT_INPUT_IO_TOGGLE_RATESpecifies the default toggle rate to be used on input I/O pins during power estimation. This value is onlyused if a

POWER_DEFAULT_TOGGLE_RATESpecifies the default toggle rate to be used on all nodes except input I/O pins during power estimation.This value is only us

POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATORSpecifies the external supply voltage applied to the on-chip voltage regulator. This option applies only todevice

POWER_HPS_DYNAMIC_POWER_DUALDynamic Power of dual processor core when HPS is active.TypeStringDevice SupportThis setting can be used in projects targe

POWER_HPS_DYNAMIC_POWER_SINGLEDynamic power of single processor core when HPS is active.TypeStringDevice SupportThis setting can be used in projects t

POWER_HPS_ENABLESpecifies whether or not you must include the HPS processor subsystem for SoC power estimation.TypeBooleanDevice SupportThis setting c

HDL_MESSAGE_LEVELSpecifies the type of HDL messages you want to view, including messages that display processing errors inthe HDL source code. 'L

POWER_HPS_JUNCTION_TEMPERATUREJunction Temperature when HPS is active.TypeStringDevice SupportThis setting can be used in projects targeting any Alter

POWER_HPS_PROC_FREQSpecifies the processor frequency of the HPS assumed by power estimation. The units for this value areMHz and the value must be pos

POWER_HPS_STATIC_POWERStatic Power when HPS is active.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.

POWER_HPS_TOTAL_POWERTotal power when HPS is active.TypeStringDevice SupportThis setting can be used in projects targeting any Altera device family.No

POWER_HSSIIf the transceivers are unused, setting this option to \"Opportunistically power off\" directs the Quartus IIsoftware to consider

POWER_HSSI_LEFTIf the transceivers on the left side of the device are unused, setting this option to \"Opportunisticallypower off\" directs

POWER_HSSI_RIGHTIf the transceivers on the right side of the device are unused, setting this option to \"Opportunisticallypower off\" direct

POWER_HSSI_VCCHIP_LEFTIf the PCI Express hard IP blocks on the left side of the device are unused, setting this option to\"Opportunistically powe

POWER_HSSI_VCCHIP_RIGHTIf the PCI Express hard IP blocks on the right side of the device are unused, setting this option to\"Opportunistically po

POWER_INPUT_FILE_NAMESpecifies the name of the VCD File or Signal Activity File which should be used to initialize the togglerates and static probabil

HDL_MESSAGE_OFFSpecifies the list of HDL message ids you want to turn off for this project.TypeIntegerDevice SupportThis setting can be used in projec

POWER_INPUT_FILE_TYPESpecifies whether the input power file is a VCD file or SAF file.TypeEnumerationValues• SAF• VCDDevice SupportThis setting can be

POWER_INPUT_SAF_NAMESpecifies the name of the Signal Activity File which should be used to initialize the toggle rates and staticprobabilities that wi

POWER_INPUT_VCD_FILE_NAMESpecifies the names of the VCD files which should be used to initialize the toggle rates and staticprobabilities that will be

POWER_OCS_VALUESpecifies the case-to-heat sink thermal resistance, in degrees Celsius per Watt, used during powerestimation.TypeStringDevice SupportTh

POWER_OJB_VALUESpecifies the junction-to-board thermal resistance, in degrees Celsius per Watt, used during powerestimation.TypeStringDevice SupportTh

POWER_OJC_VALUESpecifies the junction-to-case-sink thermal resistance, in degrees Celsius per Watt, used during powerestimation.TypeStringDevice Suppo

POWER_OSA_VALUESpecifies the heat sink-to-ambient thermal resistance, in degrees Celsius per Watt, used during powerestimation.TypeStringDevice Suppor

POWER_OUTPUT_SAF_NAMESpecifies the name the Signal Activity File should be written to containing the toggle rates and staticprobabilities used during

POWER_PRESET_COOLING_SOLUTIONSpecifies the preset cooling solution used during power estimation.TypeStringDevice SupportThis setting can be used in pr

POWER_READ_INPUT_FILEAssigns user-defined power input file characteristics to an entity. To specify a power input file, you mustdefine a named group o