Altera SerialLite III Streaming MegaCore Function Manual de usuario descargar pdf (Pagina 50)

Signal Width

Clock Domain

Direction Description

sync_tx

Standard

clocking:

user_clock

Advanced

clocking:

core_clock

Input The sync vector is an 8 bit bus. The data

value at the start of a burst and at the end of a

burst are captured and transported across the

link.

Note: This vector is not associated with

Interlaken channelization or flow

control schemes.

valid_tx

Standard

clocking:

user_clock

Advanced

clocking:

core_clock

Input This vector indicates that the data is valid.

start_of_burst_

Standard

clocking:

user_clock

Advanced

clocking:

core_clock

Input When the core is in burst mode operation,

assertion of this signal indicates that the

information on the data vector is the

beginning of a burst.

Because continuous mode is one long burst,

in this mode the signal is asserted only once

at the start of the data.

end_of_burst_tx

Standard

clocking:

user_clock

Advanced

clocking:

core_clock

Input When the core is in burst mode operation,

assertion of this signal indicates that the

information on the data vector is the end of a

burst.

4-26

Signals

UG-01126

2015.05.04

Altera Corporation

SerialLite III Streaming IP Core Functional Description

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Altera SerialLite III Streaming MegaCore Function Manual de usuario Pagina 50

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