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Chapter 5: Signals 5–13
Transport and Logical Layer Signals
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Avalon-ST Pass-Through Interface Signals
Table 5–19 through Table 5–21 list the standard Avalon-ST pass-through interface
signals.
1 When you instantiate the IP core with Qsys, these signals are automatically connected
and are not visible as inputs or outputs of the system.
io_s_wr_byteenable[m:0]
Input Input/Output slave byte enable.
io_s_wr_burstcount[k:0]
Input Input/Output slave burst count.
Table 5–16. Input/Output Slave Datapath Write Avalon-MM Interface Signals (Part 2 of 2)
Signal Direction Description
Table 5–17. Input/Output Slave Datapath Read Avalon-MM Interface Signals
Signal Direction Description
io_s_rd_clk
Input
This signal is not used, therefore it can be left open. The Avalon clock is
used internally as the clock reference for this interface.
io_s_rd_chipselect
Input Input/Output slave chip select.
io_s_rd_waitrequest
Output Input/Output slave wait request.
io_s_rd_read
Input Input/Output slave read enable.
io_s_rd_address[j:0]
Input
Input/Output slave address bus. In 1x variations, this address is a word
address (addresses a 4-byte (32-bit) word), not a byte address. In 2x
and 4x variations, this address is a double-word address (addresses an
8-byte (64-bit) word).
io_s_rd_readdata[n:0]
Output Input/Output slave read data bus.
io_s_rd_readdatavalid
Output Input/Output slave read data valid.
io_s_rd_burstcount[k:0]
Input Input/Output slave burst count.
io_s_rd_readerror
Output
Input/Output slave read error indicates that the burst read transfer did
not complete successfully. This signal is valid only when the
io_s_rd_readdatavalid
signal is asserted.
Table 5–18. Doorbell Message Avalon-MM Slave Interface Signals
Signal Direction Description
drbell_s_clk
Input
This signal is not used, therefore it can be left open. The Avalon clock
is used internally as the clock reference for this interface.
drbell_s_chipselect
Input Doorbell chip select
drbell_s_write
Input Doorbell write enable
drbell_s_read
Input Doorbell read enable
drbell_s_address[3:0]
Input
Doorbell address bus. This address is a word address (addresses a 4-
byte (32-bit) word), not a byte address.
drbell_s_writedata[31:0]
Input Doorbell write data bus
drbell_s_readdata[31:0]
Output Doorbell read data bus
drbell_s_waitrequest
Output Doorbell wait request
drbell_s_irq
Output Doorbell interrupt
- User Guide 1
- RapidIO MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbenches 6
- Releases 10
- RapidIO IP Core Features 10
- Features 11
- Device Family Support 12
- Note to Table 1–2: 13
- Interoperability Testing 14
- Note to Table 1–4: 16
- Notes to Table 1–7: 18
- Notes to Table 1–8: 19
- Installation and Licensing 20
- 2. Getting Started 23
- Simulating IP Cores 26
- Calibration Clock 27
- Transceiver Settings 28
- IV GX Variations 28
- External Transceiver PLL 29
- Specifying Constraints 30
- Variations 32
- Core Instances 34
- Mode Selection 37
- Transceiver Selection 38
- Baud Rate 39
- Reference Clock Frequency 39
- Receive Buffer Size 39
- Transmit Buffer Size 39
- Enable 16-Bit Device ID Width 40
- Destination ID Checking 40
- Maintenance Logical Layer 41
- Port Write Tx Enable 42
- Port Write Rx Enable 42
- Avalon-MM Master 43
- Avalon-MM Slave 43
- Doorbell Slave 43
- Device ID 44
- Vendor ID 44
- Revision ID 44
- Processing Element Features 45
- Switch Support 45
- Enable Switch Support 46
- Number of Ports 46
- Port Number 46
- Source Operation 46
- Destination Operation 46
- 4. Functional Description 47
- Interfaces 48
- Avalon System Clock 49
- Reference Clock 50
- Other Input Clocks 51
- Clock Domains 51
- Notes to Figure 4–2: 52
- Notes to Table 4–2: 52
- Reset for RapidIO IP Cores 53
- Reset Controller 54
- Clocking and Reset Structure 55
- Physical Layer 56
- Physical Layer Architecture 57
- Receiver Transceiver 58
- CRC Checking and Removal 58
- Transmitter Transceiver 59
- Physical Layer Receive Buffer 60
- Transport Layer 65
- Receiver 66
- Transaction ID Ranges 67
- Concentrator Register Module 69
- Maintenance Module 72
- Maintenance Register 74
- Maintenance Slave Processor 74
- Maintenance Master Processor 76
- Port-Write Processor 78
- Registers Location 81
- Transactions 82
- Notes to Table 4–8: 84
- Notes to Table 4–9: 85
- Note to Figure 4–22: 91
- Notes to Table 4–11: 95
- Notes to Table 4–12: 96
- Note to Table 4–13: 96
- Notes to Table 4–14: 97
- Doorbell Module Block Diagram 99
- Preserving Transaction Order 100
- Doorbell Message Generation 101
- Doorbell Message Reception 102
- Note to Figure 4–30: 103
- 29’hb4b5959 104
- CRC field is not removed 105
- Note to Table 4–15: 105
- Logical Layer Modules 106
- Protocol Violations 108
- Fatal Errors 108
- Maintenance Avalon-MM Slave 109
- Maintenance Avalon-MM Master 110
- Port-Write Reception Module 111
- Input/Output Avalon-MM Slave 111
- Input/Output Avalon-MM Master 112
- Note to Table 5–2: 115
- 5–2 Chapter 5: Signals 116
- Physical Layer Signals 116
- Multicast Event Signals 117
- Note to Table 5–6: 118
- Notes to Table 5–7: 118
- Chapter 5: Signals 5–5 119
- 5–6 Chapter 5: Signals 120
- Notes to Table 5–8: 121
- 5–8 Chapter 5: Signals 122
- Chapter 5: Signals 5–9 123
- Register-Related Signals 124
- Avalon-MM Interface Signals 124
- Chapter 5: Signals 5–11 125
- 4x variations 126
- 2x and 4x variations 126
- Chapter 5: Signals 5–13 127
- Note to Table 5–19: 128
- Notes to Table 5–20: 129
- 5–16 Chapter 5: Signals 130
- Notes to Table 5–21: 131
- 5–18 Chapter 5: Signals 132
- 6. Software Interface 133
- Physical Layer Registers 136
- Note to Table 6–10: 141
- Note to Table 6–11: 143
- Note to Table 6–12: 143
- Note to Table 6–13: 144
- Note to Table 6–14: 144
- Note to Table 6–15: 144
- Note to Table 6–16: 145
- Note to Table 6–17: 145
- Notes to Table 6–18: 146
- Notes to Table 6–19: 147
- Note to Table 6–22: 148
- Note to Table 6–23: 148
- Note to Table 6–24: 148
- Receive Maintenance Registers 149
- Transmit Port-Write Registers 150
- Receive Port-Write Registers 151
- Note to Table 6–45: 154
- Note to Table 6–51: 156
- Doorbell Message Registers 158
- Note to Table 6–63: 160
- 7. Testbenches 163
- 7–2 Chapter 7: Testbenches 164
- Chapter 7: Testbenches 7–3 165
- 7–4 Chapter 7: Testbenches 166
- SWRITE Transactions 167
- NWRITE_R Transactions 168
- NWRITE Transactions 169
- NREAD Transactions 170
- Doorbell Transactions 170
- Chapter 7: Testbenches 7–9 171
- Port-Write Transactions 172
- Chapter 7: Testbenches 7–11 173
- 7–12 Chapter 7: Testbenches 174
- 8. Qsys Design Example 175
- Running Qsys 177
- Adding the Master I/O BFM 181
- Adding the On-Chip Memory 182
- Connecting Unconnected Clocks 183
- Connecting System Components 183
- Generating the System 185
- Simulating the System 186
- A. Initialization Sequence 187
- Additional Information 193
- Info–2 Additional Information 194
- Document Revision History 194
- Additional Information Info–3 195
- Info–4 Additional Information 196
- Note to Table: 197
- Typographic Conventions 198
- Info–6 Additional Information 198
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