Altera PCI Compiler Manual de usuario Pagina 95
- Pagina / 360
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Altera Corporation User Guide Version 11.1 3–21
October 2011
Functional Description
lt_rdyn
Input Low
Local target ready. The local side asserts
lt_rdyn to indicate
a valid data input during target read, or ready to accept data
input during a target write. During a target read,
lt_rdyn
deassertion suspends the current transfer (i.e., a wait state is
inserted by the local side). During a target write, an inactive
lt_rdyn signal directs the PCI MegaCore function to insert
wait states on the PCI bus. The only time the function inserts
wait states during a burst is when
lt_rdyn inserts wait states
on the local side.
lt_rdyn is sampled one clock cycle before actual data is
transferred on the local side. During target write transactions,
lt_rdyn has also special functionality. To allow the local side
ample time to issue a retry for the write cycle, the PCI
MegaCore function does not assert
trdyn in the first data
phase unless the local side asserts
lt_rdyn. In this case, the
local side asserts
lt_rdyn to indicate that it intends to
complete at least one data phase and it is not going to issue a
retry.
Refer to the “Additional Design Guidelines for Target
Transactions” on page 3–88 section for additional information
about the
lt_rdyn functionality.
lt_framen
Output Low
Local target frame request. The
lt_framen output is
asserted while the PCI MegaCore function is requesting
access to the local side. It is asserted one clock cycle before
the function asserts
devseln, and it is released after the last
data phase of the transaction is transferred to/from the local
side.
lt_ackn
Output Low
Local target acknowledge. The PCI function asserts
lt_ackn
to indicate valid data output during a target write, or ready to
accept data during a target read. During a target read, an
inactive
lt_ackn indicates that the function is not ready to
accept data and local logic should delay the bursting operation.
During a target write,
lt_ackn de-assertion suspends the
current transfer (i.e., a wait state is inserted by the PCI master).
The
lt_ackn signal is only inactive during a burst when the
PCI bus master inserts wait states.
lt_dxfrn
Output Low Local target data transfer. The PCI MegaCore function asserts
the
lt_dxfrn signal when a data transfer on the local side is
successful during a target transaction.
Table 3–7. Target Signals Connecting to the Local Side (Part 2 of 3)
Name Type Polarity Description
- PCI Compiler 1
- User Guide 1
- UG-PCICOMPILER-4.12 3
- Chapter 2. Parameter Settings 6
- Chapter 4. Testbench 7
- Chapter 5. Getting Started 8
- Chapter 6. Parameter Settings 8
- Chapter 8. Testbench 10
- Additional Information 11
- Contents 12
- About PCI Compiler 13
- Release 14
- Information 14
- Device Family 14
- Features 15
- General 17
- Description 17
- PCI Testbench 18
- General Description 20
- Selecting the 21
- Appropriate 21
- Flow for Your 21
- Compliance 22
- Performance 23
- Utilization 23
- Installation and 29
- Licensing 29
- <path> 30
- OpenCore Plus Evaluation 31
- Installation and Licensing 32
- Section I. PCI Compiler 33
- With MegaWizard Plug-In 33
- Manager Flow 33
- 1. Getting Started 35
- PCI MegaCore 36
- Function Design 36
- Launch IP Toolbench 38
- Step 1: Parameterize 39
- Step 2: Set Up Simulation 41
- Step 3: Generate 41
- The Quartus II 46
- Simulation Files 46
- Master Simulation Files 47
- Target Simulation Files 49
- PCI Timing 52
- Using the 53
- Reference 53
- Designs 53
- Using the Reference Designs 58
- 2. Parameter Settings 59
- Advanced PCI 61
- MegaCore 61
- Function 61
- Master Features 62
- Variation File 65
- Parameters 65
- HARDWIRE_BARn 67
- HARDWIRE_EXP_ROM 67
- MAX_64_BAR_RW_BITS 68
- NUMBER_OF_BARS 68
- ENABLE_BITS 68
- INTERRUPT_PIN_REG 69
- PCI_66MHZ_CAPABLE 69
- HARDWIRE_BARn_ENA 69
- HARDWIRE_EXP_ROM_ENA 69
- EXP_ROM_ENA 69
- CAP_LIST_ENA 70
- CIS_PTR_ENA 70
- INTERRUPT_ACK_ENA 70
- INTERNAL_ARBITER_ENA (1) 70
- MW_CBEN_ENA 73
- Variation File Parameters 74
- 3. Functional Description 75
- PCI Bus Signals 85
- "). The signals lm_ackn 93
- Target Local-Side Signals 94
- Master Local-Side Signals 98
- PCI Bus 101
- Commands 101
- Configuration 102
- Registers 102
- Vendor ID Register 105
- Device ID Register 105
- Command Register 106
- Status Register 107
- Revision ID Register 108
- Class Code Register 109
- Cache Line Size Register 109
- Latency Timer Register 110
- Header Type Register 110
- Base Address Registers 111
- Reserved 113
- CardBus CIS Pointer Register 114
- Subsystem Vendor ID Register 114
- Subsystem ID Register 115
- Capabilities Pointer 116
- Interrupt Line Register 116
- Interrupt Pin Register 117
- Minimum Grant Register 117
- Target Mode 118
- Operation 118
- October 2011 119
- Functional Description 119
- Target Read Transactions 122
- PCI Compiler October 2011 124
- Target Mode Operation 124
- Note Figure 3–7: 124
- Clock Cycle Event 125
- Note to Figure 3–8: 128
- Note to Figure 3–9: 129
- Note to Figure 3–10: 130
- Note to Figure 3–12: 134
- I/O Read Transactions 135
- Target Write Transactions 137
- Note to Figure 3–15: 138
- Note to Figure 3–16: 142
- Note to Figure 3–17: 143
- Note to Figure 3–18: 144
- Note to Figure 3–19: 146
- Note to Figure 3–20: 148
- I/O Write Transactions 149
- Note to Figure 3–23: 152
- Disconnect 153
- Note to Figure 3–24: 154
- Note to Figure 3–25: 155
- Note to Figure 3–26: 156
- Note to Figure 3–27: 157
- Target Abort 160
- Note to Figure 3–30: 161
- Master Mode 162
- Master Mode Operation 164
- PCI Bus Parking 166
- Master Read Transactions 167
- Notes to Figure 3–31: 169
- Note to Figure 3–32: 173
- Notes to Figure 3–33: 174
- Notes to Figure 3–34: 176
- Notes to Figure 3–35: 178
- Note to Figure 3–36: 179
- Master Write Transactions 182
- Notes to Figure 3–38: 184
- Note to Figure 3–39: 188
- Notes to Figure 3–40: 189
- Notes to Figure 3–41: 191
- Notes to Figure 3–42: 193
- Note to Figure 3–43: 194
- Latency Timer Expires 199
- Disconnect Without Data 200
- Disconnect with Data 200
- Master Abort 200
- Host Bridge 201
- Host Bridge Operation 202
- Note to Figure 3–46: 202
- Note to Figure 3–47: 204
- Addressing 205
- Dual Address 205
- Cycle (DAC) 205
- 4. Testbench 211
- File(1) Description 213
- Testbench 216
- Specifications 216
- PROCEDURES and TASKS Sections 217
- Refer to the 218
- INITIALIZATION Section 218
- USER COMMANDS Section 218
- FILE IO section 223
- PROCEDURES and TASKS sections 223
- Bus Monitor (monitor) 224
- Clock Generator (clk_gen) 224
- Local Reference 225
- Description 226
- Local Target 227
- DMA Engine 227
- Local Master 229
- Prefetch 229
- LPM RAM 229
- Simulation Flow 230
- October 2011 PCI Compiler 231
- Section II. PCI Compiler 233
- With SOPC Builder Flow 233
- 5. Getting Started 235
- Builder Flow 236
- Walkthrough 236
- Set Up the PCI-Avalon Bridge 239
- Getting Started 241
- Simulate the 245
- Compile the 247
- Program a 248
- Upgrading 249
- Systems from a 249
- Previous 249
- Program a Device 250
- 6. Parameter Settings 251
- System Options-1 252
- PCI Target Performance 253
- PCI Master Performance 255
- Value of 256
- Multiple 256
- Pending Reads 256
- Interconnect 257
- Options-2 259
- PCI Bus Arbiter 260
- Parameter Settings 263
- PCI Configuration 264
- 0 . . . 0 265
- 0 AV BASE 265
- X X X X X . . . X 265
- Avalon Configuration 268
- 7. Functional Description 269
- PCI-Avalon Bridge Blocks 270
- Avalon-MM Ports 271
- PCI MegaCore Function 273
- PCI Operational Modes 274
- Functional Overview 276
- ■ PCI Host-Bridge Device mode 277
- Performance Profiles 279
- Target Performance 280
- Master Performance 280
- Interface 281
- PCI Bus Arbiter Signals 282
- PCI Target 283
- Non-Prefetchable Operations 285
- I/O Write Operations 287
- PCI Target Operation 288
- Prefetchable Operations 289
- Prefetchable Write Operations 290
- Prefetchable Read Operations 291
- PCI Master 295
- Avalon-to-PCI Write Requests 299
- Avalon-to-PCI Read Requests 300
- PCI Master Operation 304
- Ordering of Requests 306
- ■ DRC—Delayed read completion 307
- PCI Host-Bridge 313
- Altera-Provided 313
- Interrupts 314
- Control & Status 315
- PCI Interrupt Status Register 317
- PCI Interrupt Enable Register 319
- PCI Mailbox Register Access 320
- “Avalon 322
- Configuration” on page 6–16 322
- Bit Name 326
- MASTER_ENABLE_CURRENT_VALUE 327
- A2P_WRITE_IN_PROGRESS 327
- INTAN_CURRENT_VALUE 327
- CraIrq_o) to be asserted 328
- 8. Testbench 331
- BAR0 x10 342
- Arbiter (arbiter) 344
- Pull Up (pull_up) 344
- Appendix A. Using PCI 347
- Constraint File Tcl Scripts 347
- Simultaneous 348
- Switching Noise 348
- Considerations 348
- Additional 349
- -no_compile 353
- -no_pinouts 353
- -pin_prefix 353
- -pin_suffix 353
- Assignments 354
- Version of PCI 354
- Compiler 354
- How to Contact 358
- Typographic 359
- Conventions 359
- Typographic Conventions 360
Relacionado con productos y manuales para Instrumentos de medición Altera PCI Compiler
Instrumentos de medición Altera QDRII SRAM Controller MegaCore Function Manual de usuario
(68 paginas)
(68 paginas)
Instrumentos de medición Altera RLDRAM II Controller MegaCore Function Manual de usuario
(62 paginas)
(62 paginas)
Instrumentos de medición Altera SerialLite III Streaming MegaCore Function Manual de usuario
(68 paginas)
(68 paginas)
Instrumentos de medición Altera Signal Integrity Development Kit, Stratix V GX Edi Manual de usuario
(52 paginas)
(52 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.193 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales