Altera PCI Compiler Manual de usuario Pagina 1

101 Innovation DriveSan Jose, CA 95134www.altera.comPCI CompilerUser GuideCompiler Version: 11.1Document Date: October 2011c The PCI Compiler is sched

x User Guide Version 11.1 Altera CorporationPCI CompilerContentsOrdering PCI-to-Avalon Operations ...

3–26 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus SignalsTable 3–10 shows definitions for the local master transaction s

Altera Corporation User Guide Version 11.1 3–27October 2011Functional DescriptionPCI Bus CommandsTable 3–11 shows the PCI bus commands that can be in

3–28 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration RegistersIn master mode, the pci_mt64 and pci_mt32 functions can

Altera Corporation User Guide Version 11.1 3–29October 2011Functional DescriptionTable 3–12 shows the defined 64-byte configuration space. The regist

3–30 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration Registersdevice ID register value on the Read-Only PCI Configura

Altera Corporation User Guide Version 11.1 3–31October 2011Functional DescriptionVendor ID RegisterVendor ID is a 16-bit read-only register that iden

3–32 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration RegistersCommand RegisterCommand is a 16-bit read/write register

Altera Corporation User Guide Version 11.1 3–33October 2011Functional DescriptionStatus RegisterStatus is a 16-bit register that provides the status

3–34 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration RegistersRevision ID RegisterRevision ID is an 8-bit read-only r

Altera Corporation User Guide Version 11.1 3–35October 2011Functional DescriptionClass Code RegisterClass code is a 24-bit read-only register divided

Altera Corporation User Guide Version 11.1 xiPCI CompilerContents-speed ...

3–36 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration RegistersLatency Timer RegisterThe latency timer register is an

Altera Corporation User Guide Version 11.1 3–37October 2011Functional DescriptionBase Address RegistersThe PCI function supports up to six BARs. Each

3–38 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration RegistersTable 3–23 shows the format of memory BARs.In addition

Altera Corporation User Guide Version 11.1 3–39October 2011Functional DescriptionFor example, if a 64-bit BAR on BARs 1 and 0 is implemented and the

3–40 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration RegistersCardBus CIS Pointer RegisterThe card information struct

Altera Corporation User Guide Version 11.1 3–41October 2011Functional DescriptionSubsystem ID RegisterThe subsystem ID register identifies the subsys

3–42 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Configuration RegistersThe PCI MegaCore functions allow you to set a default e

Altera Corporation User Guide Version 11.1 3–43October 2011Functional Descriptionformat of the Interrupt Line Register.1 The interrupt pin can be ena

3–44 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationMaximum Latency RegisterThe maximum latency register is a

Altera Corporation User Guide Version 11.1 3–45October 2011Functional DescriptiontrdynvvvvstopnvvvvperrnvvvvserrnvvvvintanvvvvLocal-Side Datapath Sig

xii User Guide Version 11.1 Altera CorporationPCI CompilerContents

3–46 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationThe pci_mt64 and pci_t64 MegaCore functions support the f

Altera Corporation User Guide Version 11.1 3–47October 2011Functional Descriptionack64n signals in the pci_mt64 and pci_t64 functions are asserted th

3–48 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationTarget Read TransactionsThis section describes the behavi

Altera Corporation User Guide Version 11.1 3–49October 2011Functional Description4. The PCI MegaCore function drives and asserts devseln (and ack64n

3–50 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationSingle-cycle Memory Read Tar get Trans acti onsFigure 3–7

Altera Corporation User Guide Version 11.1 3–51October 2011Functional DescriptionTable 3–35 shows the sequence of events for a 64-bit single-cycle me

3–52 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode Operation1 The local-side design must ensure that PCI latency rule

Altera Corporation User Guide Version 11.1 3–53October 2011Functional DescriptionBurst Memory Read Target TransactionsThe sequence of events for a bu

3–54 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–8. Zero-Wait State Burst Memory Read Target Tran

Altera Corporation User Guide Version 11.1 3–55October 2011Functional DescriptionFigure 3–9 shows the same transaction as in Figure 3–8 with the PCI

Altera Corporation User Guide Version 11.1 1October 2011About PCI CompilerIntroductionThe Altera® PCI Compiler provides many options for creating cu

3–56 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–10 shows the same transaction as shown in Figure

Altera Corporation User Guide Version 11.1 3–57October 2011Functional DescriptionMismatched Bus Width Memory Read Target TransactionsThe following de

3–58 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–11 shows that the local side transfers a full QW

Altera Corporation User Guide Version 11.1 3–59October 2011Functional DescriptionFigure 3–12 shows a 32-bit PCI side and 64-bit local side burst memo

3–60 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–12. 32-Bit PCI and 64-Bit Local-Side Burst Memor

Altera Corporation User Guide Version 11.1 3–61October 2011Functional DescriptionI/O Read TransactionsI/O read transactions by definition are 32 bits

3–62 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationConfiguration Read TransactionsConfiguration read transac

Altera Corporation User Guide Version 11.1 3–63October 2011Functional DescriptionTarget Write TransactionsThis section describes the behavior of the

3–64 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationSingle-cycle Memory Write Targ e t Tr a nsactio n sFigur

Altera Corporation User Guide Version 11.1 3–65October 2011Functional DescriptionTable 3–36 shows the sequence of events for a 64-bit single-cycle me

2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Release InformationRelease InformationTable 1 provides information about this rel

3–66 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode Operation7The rising edge of clock cycle 7 registers the valid dat

Altera Corporation User Guide Version 11.1 3–67October 2011Functional DescriptionBurst Memory Write Target TransactionsThe sequence of events in a bu

3–68 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–16. Zero-Wait State Burst Memory Write Target Tr

Altera Corporation User Guide Version 11.1 3–69October 2011Functional DescriptionFigure 3–17 shows the same transaction as in Figure 3–16 with the PC

3–70 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–18 shows the same transaction as in Figure 3–16

Altera Corporation User Guide Version 11.1 3–71October 2011Functional DescriptionMismatched Bus-Width Memory Write Target TransactionsThe following d

3–72 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationIn Figure 3–19, the local-side transfer occurs in clock c

Altera Corporation User Guide Version 11.1 3–73October 2011Functional DescriptionFigure 3–20 shows a 32-bit burst memory write transaction; the event

3–74 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–20. 32-Bit PCI & 64-Bit Local-Side Burst Mem

Altera Corporation User Guide Version 11.1 3–75October 2011Functional DescriptionI/O Write TransactionsI/O write transactions by definition are 32 bi

Altera Corporation User Guide Version 11.1 3October 2011 About PCI CompilerTable 2 shows the level of support offered by the User Guide MegaCore func

3–76 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationConfiguration Write TransactionsConfiguration write trans

Altera Corporation User Guide Version 11.1 3–77October 2011Functional DescriptionTarget Transaction TerminationsFor all transactions except configura

3–78 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–23. Target RetryNote to Figure 3–23:(1) This sig

Altera Corporation User Guide Version 11.1 3–79October 2011Functional DescriptionDisconnectA PCI target can signal a disconnect by asserting stopn an

3–80 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–24 shows an example of a disconnect during a bur

Altera Corporation User Guide Version 11.1 3–81October 2011Functional DescriptionFigure 3–25 shows an example of a disconnect during a burst target w

3–82 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–26 shows an example of a disconnect during a bur

Altera Corporation User Guide Version 11.1 3–83October 2011Functional DescriptionFigure 3–27 shows an example of a disconnect during a burst target r

3–84 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationFigure 3–28 shows an example of a disconnect during a 32-

Altera Corporation User Guide Version 11.1 3–85October 2011Functional DescriptionFigure 3–27 shows an example of a disconnect during a 32-bit read on

4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Features IP functional simulation models enable simulation of a register transfe

3–86 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Target Mode OperationTarget AbortTarget abort refers to an abnormal terminatio

Altera Corporation User Guide Version 11.1 3–87October 2011Functional DescriptionFigure 3–30. Target AbortNote to Figure 3–30:(1) This signal is not

3–88 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationAdditional Design Guidelines for Target TransactionsAlter

Altera Corporation User Guide Version 11.1 3–89October 2011Functional DescriptionPCI MegaCore function. Table 3–37. PCI MegaCore Function Signals (P

3–90 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationThe PCI MegaCore functions support both 64-bit and 32-bit

Altera Corporation User Guide Version 11.1 3–91October 2011Functional DescriptionThe pci_mt64 and pci_mt32 functions support the following 32-bit PCI

3–92 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationThe pci_mt64 and pci_mt32 functions can generate transact

Altera Corporation User Guide Version 11.1 3–93October 2011Functional DescriptionMaster Read TransactionsThis section describes the behavior of the P

3–94 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode Operation4. A turn-around cycle on the ad bus occurs during the cl

Altera Corporation User Guide Version 11.1 3–95October 2011Functional DescriptionBurst Memory Read Master TransactionsFigure 3–31 shows the waveform

Altera Corporation User Guide Version 11.1 5October 2011 About PCI Compiler Hard-coded (fixed) or run-time configurable (dynamic) Avalon-to-PCI addr

3–96 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationTable 3–38 shows the sequence of events for a 64-bit zero

Altera Corporation User Guide Version 11.1 3–97October 2011Functional Description7The function asserts irdyn to inform the target that the function i

3–98 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode Operation10Because lm_lastn was asserted and a data phase was comp

Altera Corporation User Guide Version 11.1 3–99October 2011Functional DescriptionFigure 3–32 shows the same transaction as in Figure 3–31, but the lo

3–100 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–33 shows the same transaction as in Figure 3–31

Altera Corporation User Guide Version 11.1 3–101October 2011Functional DescriptionThe local side deasserts lm_rdyn in clock cycle 9. Consequently, on

3–102 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–34. Burst Memory Read Master Transaction with P

Altera Corporation User Guide Version 11.1 3–103October 2011Functional DescriptionSingle-Cycle Memory Read Master TransactionFigure 3–35 shows a 64-b

3–104 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–35. 64-Bit Single-Cycle Memory Read Master Tran

Altera Corporation User Guide Version 11.1 3–105October 2011Functional DescriptionFigure 3–36 shows a 32-bit single cycle memory read master transact

6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011General DescriptionTo ensure timing and protocol compliance, the PCI MegaCore fun

3–106 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationMismatched Bus Width Burst Memory Read Master Transactio

Altera Corporation User Guide Version 11.1 3–107October 2011Functional DescriptionFigure 3–37. 32-Bit PCI & 64-Bit Local Side Burst Memory Read M

3–108 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationMaster Write TransactionsThis section describes the beha

Altera Corporation User Guide Version 11.1 3–109October 2011Functional Description3. The PCI function begins the PCI address phase. During the PCI ad

3–110 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationBurst Memory Write Master TransactionsFigure 3–38 shows

Altera Corporation User Guide Version 11.1 3–111October 2011Functional DescriptionTable 3–39 shows the sequence of events for a 64-bit zero-wait stat

3–112 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode Operation6 The PCI MegaCore function begins the 64-bit memory wri

Altera Corporation User Guide Version 11.1 3–113October 2011Functional Description9Because irdyn and trdyn are asserted, the second 64-bit data word

3–114 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–39 shows the same transaction as in Figure 3–42

Altera Corporation User Guide Version 11.1 3–115October 2011Functional DescriptionFigure 3–40 shows the same transaction as in Figure 3–38 but with t

Altera Corporation User Guide Version 11.1 7October 2011 About PCI CompilerFigure 1 shows a PCI-to-DDR2 SDRAM controller interface design using the P

3–116 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–41 shows the same transaction as in Figure 3–38

Altera Corporation User Guide Version 11.1 3–117October 2011Functional DescriptionFigure 3–41. Burst Memory Write Master Transaction with PCI Wait St

3–118 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationMegaCore Function Features page of the Parameterize - PC

Altera Corporation User Guide Version 11.1 3–119October 2011Functional DescriptionFigure 3–42. Burst Memory Write Master Transaction with Variable By

3–120 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–43. 32-Bit PCI & 32-Bit Local-Side Single-C

Altera Corporation User Guide Version 11.1 3–121October 2011Functional Description64-Bit Single Cycle Memory Write Master TransactionsThis section is

3–122 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–44. PCI 64-Bit Single-Cycle Master Memory Write

Altera Corporation User Guide Version 11.1 3–123October 2011Functional DescriptionMismatched Bus Width Burst Memory Write Master TransactionsThis sec

3–124 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationFigure 3–45. 32-Bit PCI & 64-Bit Local-Side Master B

Altera Corporation User Guide Version 11.1 3–125October 2011Functional DescriptionAbnormal Master Transaction TerminationAn abnormal transaction term

i–ii User Guide Version 11.1 Altera CorporationPCI Compiler

8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011General DescriptionFor example, Figure 2 shows the PCI-to-DDR2 SDRAM design using

3–126 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Master Mode OperationDisconnect Without DataThe target device issues a discon

Altera Corporation User Guide Version 11.1 3–127October 2011Functional DescriptionHost Bridge OperationThis section describes using the pci_mt64 and

3–128 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Host Bridge OperationFigure 3–46. Configuration Read from Internal Configura

Altera Corporation User Guide Version 11.1 3–129October 2011Functional DescriptionPCI Configuration Write Transaction from the pci_mt64 Local Master

3–130 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Host Bridge OperationFigure 3–47. Configuration Write to Internal Configurati

Altera Corporation User Guide Version 11.1 3–131October 2011Functional Description64-Bit Addressing, Dual Address Cycle (DAC)This section describes a

3–132 User Guide Version 11.1 Altera CorporationPCI Compiler October 201164-Bit Addressing, Dual Address Cycle (DAC)64-Bit Address, 64-Bit Data Single

Altera Corporation User Guide Version 11.1 3–133October 2011Functional DescriptionFigure 3–48. 64-Bit Address, 64-Bit Data Single-Cycle Target Read T

3–134 User Guide Version 11.1 Altera CorporationPCI Compiler October 201164-Bit Addressing, Dual Address Cycle (DAC)Master Mode OperationA master oper

Altera Corporation User Guide Version 11.1 3–135October 2011Functional DescriptionFigure 3–49. 64-Bit Address, 64-Bit Data Master Burst Memory Read T

Altera Corporation User Guide Version 11.1 9October 2011 About PCI CompilerSelecting the Appropriate Flow for Your DesignTable 3 summarizes the guide

3–136 User Guide Version 11.1 Altera CorporationPCI Compiler October 201164-Bit Addressing, Dual Address Cycle (DAC)

Altera Corporation User Guide Version 11.1 4–1October 20114. TestbenchGeneral DescriptionThe Altera PCI testbench facilitates the design and verifica

4–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011FeaturesFeaturesThe PCI testbench includes the following features: Easy to use

Altera Corporation User Guide Version 11.1 4–3October 2011 PCI CompilerTestbenchTable 4–1 gives a description of the PCI testbench source files provi

4–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Testbench FilesTable 4–2 describes the reference design files provided in t

Altera Corporation User Guide Version 11.1 4–5October 2011 PCI CompilerTestbenchRefer to “Simulation Flow” on page 4–20 for more information on the m

4–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench SpecificationsTestbench SpecificationsThis section describes the modu

Altera Corporation User Guide Version 11.1 4–7October 2011 PCI CompilerTestbenchTable 4–5 shows the testbench's target termination support. The

4–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench SpecificationsThe bus monitor informs the master transactor of a succ

Altera Corporation User Guide Version 11.1 4–9October 2011 PCI CompilerTestbenchcfg_rdThe cfg_rd command performs single-cycle PCI configuration read

10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Compliance SummaryPCI Compiler With MegaWizard Plug-in Manager Flow This section

4–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench Specifications The mem_wr_32 command performs a burst-cycle 32-bit

Altera Corporation User Guide Version 11.1 4–11October 2011 PCI CompilerTestbenchmem_wr_64The mem_wr_64 command performs a memory write of the data t

4–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench Specificationsio_wrThe io_wr command performs a single-cycle memory

Altera Corporation User Guide Version 11.1 4–13October 2011 PCI CompilerTestbenchany address that is within the BAR1 range results in an io_hit actio

4–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench Specificationsin the PCI transactions as required by your applicatio

Altera Corporation User Guide Version 11.1 4–15October 2011 PCI CompilerTestbenchArbiter (arbiter)This module simulates the PCI bus arbiter. The modu

4–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Local Reference DesignFigure 4–3. Local Reference DesignNote to Figure 4–3:(1)

Altera Corporation User Guide Version 11.1 4–17October 2011 PCI CompilerTestbenchLocal TargetThe local target consists of a simple state machine that

4–18 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Local Reference DesignThe dma_bc_la register location includes the following 3

Altera Corporation User Guide Version 11.1 4–19October 2011 PCI CompilerTestbenchLocal MasterThe DMA engine triggers the local master. The local mast

Altera Corporation User Guide Version 11.1 11October 2011 About PCI Compilerhost bridge, Ethernet network adapter, and video card. The Altera PCI Meg

4–20 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Simulation FlowSimulation FlowThis section describes the simulation flow using

Altera Corporation User Guide Version 11.1 4–21October 2011 PCI CompilerTestbench4. Modify the target transactor model memory range. The target trans

4–22 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Simulation Flow

Altera Corporation Section II–1October 2011 Section II. PCI CompilerWith SOPC Builder FlowThe PCI Compiler with SOPC Builder flow option allows yo

Section II–2 User Guide 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler With SOPC Builder Flow

Altera Corporation User Guide Version 11.1 5–1October 20115. Getting StartedDesign FlowTo create a PCI system that uses the PCI Compiler with SOPC B

5–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler with SOPC Builder Flow Design WalkthroughAfter you have purchased

Altera Corporation User Guide Version 11.1 5–3October 2011 PCI CompilerGetting StartedFigure 5–1. System Generated Using SOPC Builder1 This walkthrou

5–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler with SOPC Builder Flow Design Walkthrough4. In the New Project Wiz

Altera Corporation User Guide Version 11.1 5–5October 2011 PCI CompilerGetting Startedc. Under Show in ‘Available device’ list, all fields should hav

12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Performance and Resource UtilizationMegaCore function. Using different parameter

5–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler with SOPC Builder Flow Design Walkthrough6. Click Next to display

Altera Corporation User Guide Version 11.1 5–7October 2011 PCI CompilerGetting StartedAdd the Remaining Components to the SOPC Builder SystemYou will

5–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler with SOPC Builder Flow Design WalkthroughComplete the Connections

Altera Corporation User Guide Version 11.1 5–9October 2011 PCI CompilerGetting Started4. From the System menu, select Auto-Assign Base Addresses.SOPC

5–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler with SOPC Builder Flow Design WalkthroughFiles Generated by SOPC

Altera Corporation User Guide Version 11.1 5–11October 2011 PCI CompilerGetting StartedSimulate the DesignSOPC Builder automatically sets up the simu

5–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler with SOPC Builder Flow Design WalkthroughYou can also copy the ms

Altera Corporation User Guide Version 11.1 5–13October 2011 PCI CompilerGetting Started Configuration read operations on command registers BAR0 and

5–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Program a Device1 You must use the -pin_suffix option for the PCI constraints

Altera Corporation User Guide Version 11.1 5–15October 2011 PCI CompilerGetting StartedUpgrading Systems from a Previous VersionFollow the steps belo

Altera Corporation User Guide Version 11.1 13October 2011 About PCI CompilerTable 6 shows PCI MegaCore function resource utilization and performance

5–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Program a Device

Altera Corporation User Guide Version 11.1 6–1October 20116. Parameter SettingsThis chapter describes the parameters available to configure PCI Compi

6–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011System Options-1Selecting the PCI Master/Target Peripheral mode results in the

Altera Corporation User Guide Version 11.1 6–3October 2011Parameter SettingsPCI Target Performance This field lists the three available PCI target pe

6–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011System Options-1In fact, if the PCI-Avalon bridge has no prefetchable BARs, it

Altera Corporation User Guide Version 11.1 6–5October 2011Parameter SettingsPCI Master Performance This field lists the two available PCI master perf

6–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Value of Multiple Pending ReadsAlthough up to four pending reads can be issued

Altera Corporation User Guide Version 11.1 6–7October 2011Parameter SettingsFigure 6–1. PCI-Avalon Bridge Burst Transfer with Multiple Pending ReadsI

6–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Value of Multiple Pending Reads6. At some point the data for R1 is returned by

Altera Corporation User Guide Version 11.1 6–9October 2011Parameter SettingsSystem Options-2 The System Options - 2 tab in the PCI Compiler wizard de

14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Performance and Resource UtilizationTable 8 lists memory utilization and perform

6–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011System Options-2The Shared PCI and Avalon Clocks option allows the PCI bus and

Altera Corporation User Guide Version 11.1 6–11October 2011Parameter Settings1 To implement a Host bridge device with no other PCI master-capable dev

6–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Configurationif the address matches one of the BARs. The PCI-Avalon bridge

Altera Corporation User Guide Version 11.1 6–13October 2011Parameter Settingsin this BAR type to 2 GBytes. In other words, this BAR type allows your

6–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI ConfigurationHardwired PCI Address—The hardwired PCI address setting allow

Altera Corporation User Guide Version 11.1 6–15October 2011Parameter SettingsThe PCI-Avalon address translation circuit requires that you supply the

6–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Avalon ConfigurationIn some cases, you should try to adjust the Base Address o

Altera Corporation User Guide Version 11.1 6–17October 2011Parameter Settings 16 if hardwired or 512 if dynamically configured 2 GBytes divided by

6–18 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Avalon Configuration

Altera Corporation User Guide Version 11.1 7–1October 20117. Functional DescriptionThis chapter provides specification details for the PCI Compiler w

Altera Corporation User Guide Version 11.1 15October 2011 About PCI CompilerTable 9 lists memory utilization and performance data for Cyclone II devi

7–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewThis section discusses: PCI-Avalon bridge module blocks PC

Altera Corporation User Guide Version 11.1 7–3October 2011Functional DescriptionFigure 7–1. Generic PCI-Avalon Bridge Block DiagramAvalon-MM PortsThe

7–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewThis port is optimized for high bandwidth transfers as a PCI

Altera Corporation User Guide Version 11.1 7–5October 2011Functional Descriptionbridge’s master ports must be connected to this port. There is no int

7–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewPCI Bus ArbiterThe PCI-Avalon bridge has an optional, integr

Altera Corporation User Guide Version 11.1 7–7October 2011Functional DescriptionFigure 7–2. PCI-Avalon Bridge Managing the PCI Target-Only Peripheral

7–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewFigure 7–3. PCI-Avalon Bridge Managing the PCI Target-Only P

Altera Corporation User Guide Version 11.1 7–9October 2011Functional DescriptionFigure 7–4. PCI-Avalon Bridge Block Diagram Managing the PCI Master/T

7–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewFigure 7–5. PCI-Avalon Bridge Managing the PCI Master/Targe

Altera Corporation User Guide Version 11.1 7–11October 2011Functional DescriptionFigure 7–6. PCI-Avalon Bridge Block Diagram Managing the PCI Host-Br

16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Performance and Resource UtilizationTable 11 lists memory utilization and perfor

7–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewWithin each of the PCI operating modes, the targeted Altera

Altera Corporation User Guide Version 11.1 7–13October 2011Functional DescriptionBurst Transfers With Single Pending Read This profile provides high

7–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Interface Signalsrequirements. If you use the PCI constraint files as recommen

Altera Corporation User Guide Version 11.1 7–15October 2011Functional DescriptionPCI Bus Commands Table 7–3 shows the PCI bus commands support for PC

7–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Target OperationPCI configuration read and write operations are automatica

Altera Corporation User Guide Version 11.1 7–17October 2011Functional Description Read requests will always be initially retried and completed as de

7–18 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Target OperationTo ensure the lowest possible latency, the PCI-Avalon brid

Altera Corporation User Guide Version 11.1 7–19October 2011Functional DescriptionI/O Write OperationsThe non-prefetchable bridge data path handles th

7–20 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Target OperationA PCI read operation handled by the non-prefetchable bridg

Altera Corporation User Guide Version 11.1 7–21October 2011Functional DescriptionTable 7–5 shows all of the termination conditions that are possible

Altera Corporation User Guide Version 11.1 17October 2011 About PCI CompilerInstallation and LicensingThe User Guide is part of the MegaCore IP Libra

7–22 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Target OperationThese features result in higher bandwidth, but introduce h

Altera Corporation User Guide Version 11.1 7–23October 2011Functional DescriptionPrefetchable Read OperationsAll prefetchable PCI read requests that

7–24 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Target OperationThe read requests are passed through the PCI-to-Avalon com

Altera Corporation User Guide Version 11.1 7–25October 2011Functional Description The PCI memory read command initiates burst transaction to the Ava

7–26 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Target OperationTable 7–8 lists the reasons for which a burst transfer can

Altera Corporation User Guide Version 11.1 7–27October 2011Functional DescriptionFigure 7–8. PCI-to-Avalon Address TranslationPCI Master Operation Th

7–28 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationThe PCI-Avalon bridge uses the burst count to select the b

Altera Corporation User Guide Version 11.1 7–29October 2011Functional Description1 Avalon-MM burst read requests are treated as if they are going to

7–30 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationFigure 7–9 shows the basic data paths and control structur

Altera Corporation User Guide Version 11.1 7–31October 2011Functional DescriptionFigure 7–9. Avalon-to-PCI Block DiagramAvalon-to-PCI Write RequestsF

Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,specific device designa

18 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Installation and LicensingFigure 3. Directory StructureqexamplesContains example

7–32 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationThe PCI-Avalon bridge will not combine multiple Avalon-MM

Altera Corporation User Guide Version 11.1 7–33October 2011Functional DescriptionSingle-cycle, 64-bit Avalon-to-PCI read requests that have only the

7–34 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationArbitration Among Pending PCI Master RequestsThe transacti

Altera Corporation User Guide Version 11.1 7–35October 2011Functional Description1 The head-of-line read command in the pending read queue is the one

7–36 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationFigure 7–10. Avalon-to-PCI Address TranslationAddress Tran

Altera Corporation User Guide Version 11.1 7–37October 2011Functional Descriptionwhether the resulting PCI address is a 32- or 64-bit address. Table

7–38 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationThe Avalon-to-PCI address translation table has two config

Altera Corporation User Guide Version 11.1 7–39October 2011Functional Description● PCI target, configuration writes are the only requests accepted, w

7–40 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationFigure 7–11. Ordering Logic for Avalon-to-PCI DirectionA2P

Altera Corporation User Guide Version 11.1 7–41October 2011Functional DescriptionTable 7–14 specifies the ordering rules and behavior of the PCI-Aval

Altera Corporation User Guide Version 11.1 19October 2011 About PCI CompilerOpenCore Plus EvaluationWith Altera’s free OpenCore Plus evaluation featu

7–42 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationOrdering PCI-to-Avalon OperationsFor requests that hit a p

Altera Corporation User Guide Version 11.1 7–43October 2011Functional DescriptionFigure 7–12. Ordering Logic for PCI-to-Avalon DirectionP2A Prefetcha

7–44 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Master OperationTable 7–15 specifies the ordering rules and behavior for t

Altera Corporation User Guide Version 11.1 7–45October 2011Functional DescriptionPCI Host-Bridge Operation You can use the PCI Host-Bridge Device ope

7–46 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011InterruptsWhen no ArbReq_n_i lines are asserted, ArbGnt_n_o[0] will be asserte

Altera Corporation User Guide Version 11.1 7–47October 2011Functional DescriptionThe Avalon-MM interrupt status register contains two bits that indic

7–48 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status RegistersBecause all accesses come from Avalon-MM (reques

Altera Corporation User Guide Version 11.1 7–49October 2011Functional DescriptionTable 7–17 shows the complete map of registers.The following section

7–50 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status RegistersTable 7–18 describes the PCI interrupt status re

Altera Corporation User Guide Version 11.1 7–51October 2011Functional DescriptionPCI Interrupt Enable RegisterBy setting the corresponding bits in th

20 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Installation and Licensing

7–52 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status RegistersAvalon-MM interrupts can also be enabled for all

Altera Corporation User Guide Version 11.1 7–53October 2011Functional DescriptionThe Avalon-to-PCI mailbox registers are readable at the addresses sh

7–54 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status RegistersThe lower order address bits that are treated as

Altera Corporation User Guide Version 11.1 7–55October 2011Functional DescriptionTable 7–23 lists some basic configuration parameters of the bridge.T

7–56 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status RegistersTable 7–24 lists some key performance sizing inf

Altera Corporation User Guide Version 11.1 7–57October 2011Functional DescriptionTable 7–26 describes the Avalon-MM interrupt status register bits.Ta

7–58 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status Registers7INTAN_RISERW1CThis bit is set to 1 when the PCI

Altera Corporation User Guide Version 11.1 7–59October 2011Functional DescriptionTable 7–27 describes the current PCI status register. This register

7–60 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status RegistersAvalon-MM Interrupt Enable RegisterAn Avalon-MM

Altera Corporation User Guide Version 11.1 7–61October 2011Functional DescriptionThe Avalon-to-PCI mailbox registers are writable at the addresses sh

Altera Corporation Section I–1October 2011 Section I. PCI CompilerWith MegaWizard Plug-InManager FlowThe Altera PCI Compiler provides a complete s

7–62 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Control & Status Registers

Altera Corporation User Guide Version 11.1 8–1October 20118. TestbenchGeneral DescriptionThe Altera PCI testbench facilitates the design and verifica

8–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011FeaturesFigure 8–1. Altera PCI Testbench Block DiagramTo use the PCI testbench,

Altera Corporation User Guide Version 11.1 8–3October 2011 PCI CompilerTestbenchPCI Testbench FilesThe Altera PCI testbench is included and installed

8–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench SpecificationsRefer to “Simulation Flow” on page 8–15 for more inform

Altera Corporation User Guide Version 11.1 8–5October 2011 PCI CompilerTestbenchTable 8–3 shows the testbench's target termination support. The

8–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench SpecificationsThe master transactor terminates the PCI transactions i

Altera Corporation User Guide Version 11.1 8–7October 2011 PCI CompilerTestbenchUSER COMMANDS SectionThe master transactor USER COMMANDS section cont

8–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench Specificationscfg_wrThe cfg_wr command performs single-cycle PCI conf

Altera Corporation User Guide Version 11.1 8–9October 2011 PCI CompilerTestbenchmem_rd_32The mem_rd_32 command performs a memory read with the addres

Section I–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Compiler With MegaWizard Plug-In Manager Flow

8–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench Specificationsmem_wr_64The mem_wr_64 command performs a memory write

Altera Corporation User Guide Version 11.1 8–11October 2011 PCI CompilerTestbenchmem_rd_64The mem_rd_64 command performs memory read transactions wit

8–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench SpecificationsTarget Transactor (trgt_tranx)The testbench target tra

Altera Corporation User Guide Version 11.1 8–13October 2011 PCI CompilerTestbenchTo model different target terminations, use the following three inpu

8–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Testbench Specifications Target retry Target abort Target terminated with d

Altera Corporation User Guide Version 11.1 8–15October 2011 PCI CompilerTestbenchSimulation FlowThis section describes the simulation flow using Alte

8–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Simulation FlowRefer to Figure 8–1 for a block diagram of the Master Transacto

Altera Corporation User Guide Version 11.1 A–1October 2011Appendix A. Using PCIConstraint File Tcl ScriptsIntroductionAltera provides constraint file

A–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Simultaneous Switching Noise (SSN) Considerations4. Source the constraint file

Altera Corporation User Guide Version 11.1 A–3October 2011 PCI Compilerf For more recommendations on reducing SSN in your design, refer to AN 315: Gu

Altera Corporation User Guide Version 11.1 1–1October 20111. Getting StartedDesign FlowTo evaluate a PCI Compiler MegaCore function using the OpenCor

A–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Additional OptionsEP2AGZ225 — -3, -4 66 MHzEP2AGZ300 -3 -3, -4 66 MHzEP2AGZ350F

Altera Corporation User Guide Version 11.1 A–5October 2011 PCI CompilerEP4CGX30BF14EP4CGX30CF19EP4CGX30CF23-6 -6, -7, -8 66 MHzEP4CGX50CF23EP4CGX50DF

A–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Additional OptionsFor constraint files that have a default value of 66 MHz, you

Altera Corporation User Guide Version 11.1 A–7October 2011 PCI Compiler-no_compileBy default, the add_pci_constraints command performs analysis and s

A–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Upgrading Assignments from a Previous Version of PCI CompilerMegaCore functions

Altera Corporation User Guide Version 11.1 A–9October 2011 PCI Compiler Manually delete all the existing PCI assignments from your QSF, then use the

A–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Upgrading Assignments from a Previous Version of PCI Compiler

Altera Corporation User Guide Version 11.1 Info–iOctober 2011Additional InformationRevision HistoryThe following table displays the revision history

Info–ii User Guide Version 11.1 Altera CorporationPCI Compiler October 2011How to Contact AlteraHow to Contact AlteraFor the most up-to-date informati

Altera Corporation User Guide Version 11.1 Info–iiiOctober 2011Typographic ConventionsThe following table shows the typographic conventions that this

1–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI MegaCore Function Design WalkthroughAfter you have purchased a license for

Info–iv User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Typographic Conventions

Altera Corporation User Guide Version 11.1 1–3October 2011 PCI CompilerGetting StartedTo create a new project, follow these steps:1. Choose Programs

1–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI MegaCore Function Design Walkthrough7. Click Next to close this page and di

Altera Corporation User Guide Version 11.1 1–5October 2011 PCI CompilerGetting Started5. The MegaWizard Plug-In Manager shows the project path that y

i–iv User Guide Version 11.1 Altera CorporationPCI Compiler

1–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI MegaCore Function Design Walkthrough4. Click Next to open the Base Address

Altera Corporation User Guide Version 11.1 1–7October 2011 PCI CompilerGetting StartedStep 2: Set Up SimulationAn IP functional simulation model is a

1–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI MegaCore Function Design WalkthroughTo generate your MegaCore function, fol

Altera Corporation User Guide Version 11.1 1–9October 2011 PCI CompilerGetting Started2. After you review the generation report, click Exit to close

1–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Simulate the DesignThis section of the walkthrough uses the following: The IP

Altera Corporation User Guide Version 11.1 1–11October 2011 PCI CompilerGetting StartedSimulation in the Quartus II SoftwareAltera provides Vector Wa

1–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011The Quartus II Simulation Files6. In the Simulation input, specify <path>

Altera Corporation User Guide Version 11.1 1–13October 2011 PCI CompilerGetting StartedMaster Simulation Files Table 1–2 describes the Quartus II sim

1–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011The Quartus II Simulation FilesTable 1–3 describes the Quartus II simulation f

Altera Corporation User Guide Version 11.1 1–15October 2011 PCI CompilerGetting StartedTarget Simulation Files Table 1–4 describes the Quartus II sim

Altera Corporation vContentsAbout PCI CompilerIntroduction ...

1–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Compile the DesignTable 1–5 describes the Quartus II simulation files included

Altera Corporation User Guide Version 11.1 1–17October 2011 PCI CompilerGetting StartedFor this walkthrough, follow these steps:1. Open <path>\

1–18 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Program a DeviceProgram a DeviceAfter you have compiled your design, program y

Altera Corporation User Guide Version 11.1 1–19October 2011 PCI CompilerGetting Started2. In the Quartus II software, choose Tcl C o n s o l e (Vie

1–20 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Using the Reference DesignsRefer to Table 1–3 the pci_mt32 MegaCore Function R

Altera Corporation User Guide Version 11.1 1–21October 2011 PCI CompilerGetting Started<path>/pci_compiler/megawizard_flow/ref_designs/pci_mt32

1–22 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Using the Reference Designs<path>/pci_compiler/megawizard_flow/ref_desig

Altera Corporation User Guide Version 11.1 1–23October 2011 PCI CompilerGetting Started<path>/pci_compiler/megawizard_flow/ref_designs/pci_mt64

1–24 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Using the Reference Designs

Altera Corporation User Guide Version 11.1 2–1October 20112. Parameter SettingsThis chapter describes the parameters available to configure PCI Compi

vi User Guide Version 11.1 Altera CorporationPCI CompilerContentsCompile the Design ...

2–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Read-Only PCI Configuration RegistersRead-Only PCI Configuration RegistersParam

Altera Corporation User Guide Version 11.1 2–3October 2011Parameter SettingsThe pci_mt64 and pci_t64 MegaCore functions allow the implementation of 6

2–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Advanced PCI MegaCore Function FeaturesOptional Interrupt CapabilitiesThe PCI M

Altera Corporation User Guide Version 11.1 2–5October 2011Parameter SettingsAllow Variable Byte Enables During Burst TransactionsIn a default master

2–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Advanced PCI MegaCore Function FeaturesDisable Master Latency TimerTurning on t

Altera Corporation User Guide Version 11.1 2–7October 2011Parameter SettingsVariation File ParametersIf you do not want to use the IP Toolbench Param

2–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Variation File ParametersVEND_IDHexadecimal H"1172" Device vendor ID

Altera Corporation User Guide Version 11.1 2–9October 2011Parameter SettingsHARDWIRE_BARnHexadecimal H"FF000000" Hardwire base address regi

2–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Variation File ParametersMAX_64_BAR_RW_BITSDecimal 8 Maximum number of read/wr

Altera Corporation User Guide Version 11.1 2–11October 2011Parameter SettingsTable 2–2 shows the bit definition for ENABLE_BITS.INTERRUPT_PIN_REGHexa

Altera Corporation User Guide Version 11.1 viiPCI CompilerContentsInterrupt Pin Register ...

2–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Variation File Parameters8CAP_LIST_ENA0 Capabilities list enable. This bit det

Altera Corporation User Guide Version 11.1 2–13October 2011Parameter Settings13SELF_CFG_HB_ENA (1)0 Host bridge enable. This bit controls the self-co

2–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Variation File Parameters15DISABLE_LAT_TMR (1)1 Disable master latency timer.

Altera Corporation User Guide Version 11.1 2–15October 2011Parameter Settings17MW_CBEN_ENA0 In a standard master burst transaction the byte enables a

2–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Variation File Parameters

Altera Corporation User Guide Version 11.1 3–1October 20113. Functional DescriptionThis chapter contains detailed information on the PCI Compiler and

3–2 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewFigure 3–1. pci_mt64 Functional Block DiagramPCI Address/Dat

Altera Corporation User Guide Version 11.1 3–3October 2011Functional DescriptionFigure 3–2. pci_mt32 Functional Block DiagramPCI Address/Data BufferP

3–4 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewFigure 3–3. pci_t64 Functional Block Diagramreq64nack64npar6

Altera Corporation User Guide Version 11.1 3–5October 2011Functional DescriptionFigure 3–4. pci_t32 Functional Block DiagramPCI Address/Data BufferPa

viii User Guide Version 11.1 Altera CorporationPCI CompilerContentsFeatures ...

3–6 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewTarget Device Signals & Signal AssertionFigure 3–5 illus

Altera Corporation User Guide Version 11.1 3–7October 2011Functional Description When both trdyn and irdyn are active, a data word is clocked from t

3–8 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewThe pci_mt64 and pci_t64 functions accept either 32-bit tran

Altera Corporation User Guide Version 11.1 3–9October 2011Functional DescriptionMaster Device Signals & Signal AssertionFigure 3–6 illustrates th

3–10 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011Functional OverviewWhen the pci_mt64 or pci_mt32 function is ready to present

Altera Corporation User Guide Version 11.1 3–11October 2011Functional DescriptionPCI Bus SignalsThe following PCI signals are used by the pci_mt64, p

3–12 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus Signalsad[63..0]Tri- Sta te –Address/data bus. The ad[63..0] bus is a

Altera Corporation User Guide Version 11.1 3–13October 2011Functional Descriptionreq64n (1)STS LowRequest 64-bit transfer. The req64n signal is an ou

3–14 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus SignalsintanOpen-Drain LowInterrupt A. The intan signal is an active-l

Altera Corporation User Guide Version 11.1 3–15October 2011Functional DescriptionParameterized Configuration Register SignalsTable 3–3 summarizes the

Altera Corporation User Guide Version 11.1 ixPCI CompilerContentsSystem Options-2 ...

3–16 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus SignalsTable 3–5 shows definitions for the PCI status register bits.Lo

Altera Corporation User Guide Version 11.1 3–17October 2011Functional DescriptionTable 3–6. PCI Local Address, Data, Command & Byte Enable Signal

3–18 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus Signalsl_adro[63..0]Output – Local address output. The l_adro[63..0] b

Altera Corporation User Guide Version 11.1 3–19October 2011Functional Descriptionl_cmdo[3..0]Output –Local command output. The l_cmdo[3..0] bus is dr

3–20 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus SignalsTarget Local-Side SignalsTable 3–7 summarizes the target interf

Altera Corporation User Guide Version 11.1 3–21October 2011Functional Descriptionlt_rdynInput LowLocal target ready. The local side asserts lt_rdyn t

3–22 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus Signalslt_tsr[11..0]Output –Local target transaction status register.

Altera Corporation User Guide Version 11.1 3–23October 2011Functional DescriptionTable 3–8 shows definitions for the local target transaction status

3–24 User Guide Version 11.1 Altera CorporationPCI Compiler October 2011PCI Bus SignalsMaster Local-Side SignalsTable 3–9 summarizes the pci_mt64 and

Altera Corporation User Guide Version 11.1 3–25October 2011Functional Descriptionlm_rdynInput LowLocal master ready. The local side asserts the lm_rd