
1–10 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Simulate the Design
This section of the walkthrough uses the following:
■ The IP toolbench-generated PCI testbench in the
c:\altera\projects\pci_project_nativelink\verilog\pci_mt64
directory
■ The IP functional simulation model generated as specified in “Step
2: Set Up Simulation” on page 1–7
■ The ModelSim
®
software
■ The generated NativeLink script in the project directory,
c:\altera\projects
For this walkthrough, follow these steps:
1. On the EDA Tool Option page in the Quartus II software (Too l s >
Options > EDA Tools Option), set the location of the ModelSim
executable .
1 If you are using other simulators, set the location of your
preferred EDA simulation tool executable. This is a global
setting, and needs to be done only once.
2. At the Quartus II Tcl Console, run the following command:
source pci_top_nativelink.tcl
3. On the Simulation page (Assignments > EDA Tools Settings >
Simulation), do the following:
● select ModelSim from the Too l N a me list
● select Compile test bench under NativeLink settings.
4. Perform analysis and synthesis to create the required netlist.
5. Run the simulation.
f For more information on simulation using NativeLink, refer to
Simulating Altera IP in Third-Party Simulation Tools chapter in volume 3 of
the Quartus II Handbook.
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