Altera Nios Development Board Cyclone II Edition Manual de usuario Pagina 50
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2–38 Reference Manual Altera Corporation
Nios Development Board Cyclone II Edition May 2007
Board Components
Flash Memory Partitions
The configuration controller expects user and factory configuration data
to be stored at fixed locations (offsets) in flash memory. In addition, the
factory-programmed reference design expects Nios II software and data
to exist at certain locations in flash memory. Table 2–20 shows the
expected flash memory partitioning.
1 This partitioning scheme is merely a convention used by the
configuration controller and the factory-programmed reference
design. Custom FPGA designs can use the flash memory space
in any way necessary.
c Altera recommends that you do not overwrite the factory-
programmed flash memory contents. Without a valid factory
configuration, the configuration controller may not be able to
successfully configure the FPGA. If you alter the factory
configuration, you can restore the board to its factory-
programmed state. Refer to Appendix B: Restoring the Factory
Configuration.
User Application Space
The lower 11 MB of flash memory is the user application space. This is
free space for user designs to store code and data for Nios II programs.
The Nios II IDE allows you to compile Nios II programs and program
them into the user application space.
Table 2–20. Flash Memory Partitions
Offset Usage Factory-Programmed Content
0x00000000 – 0x00BFFFFF User Application Space (11 MB)
0x00C00000 – 0x00CFFFFF User Configuration (1 MB)
0x00D00000 –0x00DFFFFFF Free Space (1 MB)
0x00E00000 – 0x00EFFFFF Factory Configuration (1 MB) Nios II Processor Reference
Design
0x00F00000 – 0x00FAFFFF Web Pages Web Pages
0x00FB0000 – 0x00FEFFFF Web Server Software Web Server Software
0x00FF0000 – 0x00FFFFFF Persistent Data Network Settings for Web Server
- Nios Development Board 1
- Part Number MNL-N051805-1.3 2
- Contents 3
- About this Manual 5
- Typographic 6
- Conventions 6
- Visual Cue Meaning 7
- 1. Overview 9
- Factory 10
- Programmed 10
- Reference 10
- Overview 11
- 2. Board Components 13
- Connections & Interfaces 14
- Configuration & Reset 14
- EP2C35 Device 15
- Cyclone II 15
- Push-Button 16
- Switches (SW0 16
- Individual LEDs 17
- (D0 - D7) 17
- Seven-Segment 17
- LEDs (U8 & U9) 17
- SSRAM Chip 18
- Table 2–6. SSRAM Pin Table 19
- DDR SDRAM 21
- Chip (U63) 21
- Flash Memory 23
- Ethernet 25
- MAC/PHY (U4) & 25
- RJ45 Connector 25
- Serial Connector 27
- Expansion 28
- Prototype 28
- Connectors 28
- (PROTO1 & 28
- Board Components 31
- F21 11 J13 proto1_pllclk 31
- N26 13 J13 proto1_clkout 31
- Notes to Figure 2–7: 32
- CompactFlash 35
- Connector 35
- PMC Connector 38
- (JH1 & JH2) 38
- Connector (J25) 41
- Test Points 43
- (TP1–TP8) 43
- EPCS64 Serial 44
- Configuration 44
- Device (U69) 44
- Controller 45
- Device (U3) 45
- SW8 – CPU Reset 46
- SW9 – Factory Config 47
- SW10 – Reset, Config 47
- Reset Distribution 48
- Starting Configuration 48
- Configuration Process 49
- Flash Memory Partitions 50
- JTAG Connectors 51
- (J24 & J5) 51
- Clock Circuitry 53
- Figure 2–21. Clock Circuitry 54
- Power-Supply 56
- Circuitry 56
- Appendix A. Restoring the 57
- Appendix B. Connecting to 59
- Connecting the LCD Screen 60
- Obtaining an IP Address 60
- LAN Connection 61
- Point–to–Point Connections 62
- Browsing to Your 63
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