Altera MAX 10 Clocking and PLL Manual de usuario Pagina 31
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You must choose the backup clock frequency and set the M, N, and C counters so that the VCO operates
within the recommended frequency range.
The following figure shows a clock switchover waveform controlled by the clkswitch signal. In this case,
both clock sources are functional and inclk0 is selected as the reference clock. The clkswitch signal goes
high, which starts the switchover sequence. On the falling edge of inclk0, the counter’s reference clock,
muxout, is gated off to prevent clock glitching. On the falling edge of inclk1, the reference clock
multiplexer switches from inclk0 to inclk1 as the PLL reference. The activeclock signal is asserted to
indicate the clock that is currently feeding the PLL, which is inclk1.
In automatic override with manual switchover mode, the activeclock signal mirrors the clkswitch
signal. Since both clocks are still functional during the manual switch, neither clkbad signal goes high.
Because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not
cause the circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again, the
process repeats.
Figure 2-22: Example of Clock Switchover Using the
clkswitch
(Manual) Control
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
To initiate a manual clock switchover event,
both inclk0 and inclk1 must be running when
the clkswitch signal goes high.
The
clkswitch signal and automatic switch work only if the clock being switched to is available. If the
clock is not available, the state machine waits until the clock is available.
Manual Clock Switchover
In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as
the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high,
and is being held high for at least three inclk cycles. You must bring the clkswitch signal back to low
again to perform another switchover event. If you do not require another switchover event, you can leave
the clkswitch signal in a logic high state after the initial switch. Pulsing the clkswitch signal high for at
least three inclk cycles performs another switchover event.
UG-M10CLKPLL
2015.05.04
Manual Clock Switchover
2-25
MAX 10 Clocking and PLL Architecture and Features
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 3
- Clock Networks Overview 5
- Internal Oscillator Overview 5
- PLLs Overview 5
- • PLL cascading 6
- • Reference clock switchover 6
- Features 7
- Clock Resources 8
- Global Clock Network Sources 8
- Pin GCLK 9
- Global Clock Control Block 10
- Input Description 11
- Related Information 12
- Clock Enable Signals 13
- PLL Architecture 14
- UG-M10CLKPLL 15
- 2015.05.04 15
- PLL Features 16
- PLL Locations 16
- Clock Pin to PLL Connections 18
- PLL Control Signals 19
- Clock Feedback Modes 20
- Source Synchronous Mode 21
- No Compensation Mode 21
- Normal Mode 22
- PLL External Clock Output 23
- ADC Clock Input from PLL 25
- Spread-Spectrum Clocking 25
- PLL Programmable Parameters 25
- Programmable Phase Shift 26
- Clock Switchover 28
- Manual Clock Switchover 31
- PLL Cascading 32
- PLL Reconfiguration 32
- Considerations 35
- PLLs Design Considerations 36
- Guideline: PLL Cascading 37
- Guideline: Clock Switchover 37
- ALTCLKCTRL IP Core 39
- Search for installed IP cores 40
- ALTPLL IP Core 43
- Block Name 50
- Number of Bits 50
- Counter Control Bit Total 50
- 3. Ignore this directory 55
- ALTPLL_RECONFIG IP Core 56
- Internal Oscillator IP Core 59
- ALTCLKCTRL IP Core References 64
- ALTCLKCTRL Ports and Signals 65
- ALTPLL IP Core References 67
- Parameter Value Description 68
- ALTPLL Ports and Signals 72
- Port Name 73
- Condition Description 73
- ALTPLL_RECONFIG Parameters 77
- Parameter Value Decription 85
- Date Version Changes 86
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