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August 2014 Altera Corporation IP Compiler for PCI Express User Guide

7. Reset and Clocks

This chapter covers the functional aspects of the reset and clock circuitry for IP

Compiler for PCI Express variations created using the IP Catalog and parameter

editor. It includes the following sections:

■ Reset Hard IP Implementation

■ Reset Soft IP Implementation

■ Clocks

For descriptions of the available reset and clock signals refer to the following sections

in the Chapter 5, IP Core Interfaces: “Reset and Link Training Signals” on page 5–24,

“Clock Signals—Hard IP Implementation” on page 5–23, and “Clock Signals—Soft IP

Implementation” on page 5–23.

Reset Hard IP Implementation

Altera provides two options for reset circuitry in the parameter editor for PCI Express

hard IP implementation. Both options are created automatically when you generate

your IP core. These options are implemented by following files:

■ <variant>_plus.v or .vhd—The variant includes the logic for reset and transceiver

calibration as part of the IP core, simplifying system development at the expense

of some flexibility. This file is stored in the <install_dir>/chaining_dma/ directory.

■ <variant>.v or .vhd—This file does not include reset or calibration logic, giving

you the flexibility to design circuits that meet your requirements. If you select this

method, you can share the channels and reset logic in a single quad with other

protocols, which is not possible with _plus option. However, you may find it

challenging to design a reliable solution. This file is stored in the <working_dir>

directory.

The reset logic for both of these variants is illustrated by Figure 7–1.

1 When you use Qsys to generate the IP Compiler for PCI Express, the reset and

calibration logic is included in the IP core variant.

<variant>_plus.v or .vhd

This option partitions the reset logic between the following two plain text files:

■ <working_dir>/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v or

.vhd—This file includes the logic to reset the transceiver.

■ <working_dir>/<variation>_examples/chaining_dma/<variation>_rs_hip.v or

.vhd—This file includes the logic to reset the IP Compiler for PCI Express.

The _plus variant includes all of the logic necessary to initialize the IP Compiler for

PCI Express, including the following logic:

■ Reset circuitry

■ ALTGXB Reconfiguration IP core

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Altera IP Compiler for PCI Express Manual de usuario Pagina 165