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Chapter 1: About the FIR Compiler 1–7
Performance and Resource Utilization
© May 2011 Altera Corporation FIR Compiler User Guide
Table 1–6 shows performance figures for Stratix IV devices:
Parallel (LE), pipeline level 1(2), (3)
3,416 3,715 208 3 — 288 288 28
Parallel (M9K), pipeline level 1 (2), (5)
1,948 2,155 120,030 48 — 283 283 27
Serial (M9K), pipeline level 1 (2), (3)
327 462 14,167 8 — 323 36 3
Notes to Table 1–5:
(1) GMAC = giga multiply accumulates per second (1 giga = 1,000 million).
(2) This FIR filter takes advantage of symmetric coefficients.
(3) Using EP3C10F256C6 devices.
(4) Using EP3C16F484C6 devices.
(5) Using EP3C40F780C6 devices.
(6) It may be possible to significantly reduce memory utilization by setting a lower target f
MAX
.
Table 1–5. FIR Compiler Performance—Cyclone III Devices (Part 2 of 2)
Combinational
LUTs
Logic
Registers
Memory (6)
Multipliers
(9x9)
f
max
(MHz)
Throughput
(MSPS)
Processing
Equivalent
(GMACs) (1)Bits M9K
Table 1–6. FIR Compiler Performance—Stratix IV Devices
Combinational
ALUTs
Logic
Registers
Memory
Multipliers
(18x18)
f
max
(MHz)
Throughput
(MSPS)
Processing
Equivalent
(GMACS) (1)Bits (M9K) ALUTs
Multibit Serial, pipeline level 1 (2), (3), (4)
766 1,166 55,276 42 16 — 503 101 10
Multicycle variable (1 cycle) decimation by 4, pipeline level 1 (2), (3)
336 844 1,400 16 28 14 443 443 43
Multicycle variable (1 cycle) interpolation by 4, pipeline level 2 (3)
200 1,274 64 — 8 24 372 372 36
Multicycle variable (1 cycle), pipeline level 2 (2), (3)
741 1,936 148 1 8 48 443 443 43
Multicycle variable (4 cycle), pipeline level 2 (2), (3)
717 1,398 796 6 36 14 323 81 8
Parallel (LE), pipeline level 1 (2), (3)
2,153 2,672 157 1 8 — 421 421 41
Parallel (M9K), pipeline level 1 (3)
821 1,730 119,872 45 8 — 457 457 44
Serial (M9K), pipeline level 1 (2), (3)
245 415 14,231 11 8 — 523 58 6
Notes to Table 1–6:
(1) GMAC = giga multiply accumulates per second (1 giga = 1,000 million).
(2) This FIR filter takes advantage of symmetric coefficients.
(3) Using EP4SGX70DF29C2X devices.
(4) The data width is 16-bits and there are 4 serial units.
- FIR Compiler 1
- User Guide 1
- UG-FIRCOMPILER 11.0 2
- Contents 3
- Additional Information 4
- 1. About the FIR Compiler 5
- Delay Line 6
- Coefficient 6
- Multipliers 6
- Adder Tree 6
- Features 7
- Release Information 8
- Device Family Support 9
- MegaCore Verification 10
- Notes to Table 1–5: 11
- Notes to Table 1–6: 11
- Installation and Licensing 12
- 2. Getting Started 15
- Figure 2–4. Set Up Simulation 18
- Notes to Table 2–1 21
- Simulate the Design 22
- Simulating in MATLAB 23
- 3. Parameter Settings 25
- Specifying the Coefficients 26
- Note to Figure 3–6: 31
- Analyzing the Coefficients 32
- Bits Removed from MSB 34
- Bits Removed from LSB 34
- Note to Table 3–4: 36
- Note to Table 3–5: 37
- Note to Table 3–6: 38
- Resource Estimates 40
- Filter Design Tips 40
- 4. Functional Description 43
- Coefficient Scaling 44
- Symmetrical Serial 45
- Structure Types 48
- Serial Structures 49
- Multibit Serial Structure 49
- Interpolation and Decimation 50
- Figure 4–8. Signal Decimation 51
- Pipelining 54
- Simulation Output 55
- Avalon Streaming Interface 55
- Data Source Data Sink 56
- Packet Data Transfers 57
- ■ 00: No error 58
- ■ 01: Missing SOP 58
- ■ 10: Missing EOP 58
- ■ 11: Unexpected EOP 58
- Timing Diagrams 59
- Referenced Documents 68
- Structures 69
- Supported Device Structures 70
- Compiling HardCopy Designs 71
- How to Contact Altera 74
- Typographic Conventions 74
- Additional Information Info–3 75
- Info–4 Additional Information 76
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