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1–6 Chapter 1: About the FIR Compiler
MegaCore Verification
FIR Compiler User Guide © May 2011 Altera Corporation
MegaCore Verification
Before releasing an updated version of the FIR Compiler, Altera runs a comprehensive
regression test to verify its quality and correctness.
All features and architectures are tested by sweeping all parameter options and
verifying that the simulation matches a master functional model.
Performance and Resource Utilization
This section shows typical expected performance for a FIR Compiler MegaCore
function with Cyclone III and Stratix IV devices. All figures are given for a FIR filter
with 97 taps, 8-bit input data, 14-bit coefficients, a target f
MAX
set to 1 GHz.
1 Cyclone III devices use combinational look-up tables (LUTs) and logic registers;
Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic
registers.
The resource and performance data was generated with the source ready signal
(ast_source_ready) always driven high, as described in “Avalon Streaming
Interface” on page 4–13.
Table 1–5 shows performance figures for Cyclone III devices:
Table 1–5. FIR Compiler Performance—Cyclone III Devices (Part 1 of 2)
Combinational
LUTs
Logic
Registers
Memory (6)
Multipliers
(9x9)
f
max
(MHz)
Throughput
(MSPS)
Processing
Equivalent
(GMACs) (1)Bits M9K
Multibit Serial, pipeline level 1 (2), (3)
899 1,331 55,148 31 — 310 62 6
Multicycle variable (1 cycle) decimation by 4, pipeline level 1 (2), (3)
857 1,336 1,158 12 26 281 281 27
Multicycle variable (1 cycle) interpolation by 4, pipeline level 2 (4)
1,528 2,657 66 1 50 290 290 28
Multicycle variable (1 cycle), pipeline level 2 (2), (4)
2,543 4,837 92 1 98 280 280 27
Multicycle variable (4 cycle), pipeline level 2 (2), (3)
1,182 1,715 578 9 26 283 71 7
- FIR Compiler 1
- User Guide 1
- UG-FIRCOMPILER 11.0 2
- Contents 3
- Additional Information 4
- 1. About the FIR Compiler 5
- Delay Line 6
- Coefficient 6
- Multipliers 6
- Adder Tree 6
- Features 7
- Release Information 8
- Device Family Support 9
- MegaCore Verification 10
- Notes to Table 1–5: 11
- Notes to Table 1–6: 11
- Installation and Licensing 12
- 2. Getting Started 15
- Figure 2–4. Set Up Simulation 18
- Notes to Table 2–1 21
- Simulate the Design 22
- Simulating in MATLAB 23
- 3. Parameter Settings 25
- Specifying the Coefficients 26
- Note to Figure 3–6: 31
- Analyzing the Coefficients 32
- Bits Removed from MSB 34
- Bits Removed from LSB 34
- Note to Table 3–4: 36
- Note to Table 3–5: 37
- Note to Table 3–6: 38
- Resource Estimates 40
- Filter Design Tips 40
- 4. Functional Description 43
- Coefficient Scaling 44
- Symmetrical Serial 45
- Structure Types 48
- Serial Structures 49
- Multibit Serial Structure 49
- Interpolation and Decimation 50
- Figure 4–8. Signal Decimation 51
- Pipelining 54
- Simulation Output 55
- Avalon Streaming Interface 55
- Data Source Data Sink 56
- Packet Data Transfers 57
- ■ 00: No error 58
- ■ 01: Missing SOP 58
- ■ 10: Missing EOP 58
- ■ 11: Unexpected EOP 58
- Timing Diagrams 59
- Referenced Documents 68
- Structures 69
- Supported Device Structures 70
- Compiling HardCopy Designs 71
- How to Contact Altera 74
- Typographic Conventions 74
- Additional Information Info–3 75
- Info–4 Additional Information 76
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