Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manual de usuario Pagina 24
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2–10 Chapter 2: Getting Started
Generated Files
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 2–5 shows the additional files generated by the high-performance controller II
that may be in your project directory.
<variation_name>_
alt_mem_phy_oc
t_delay
DDR2/DDR SDRAM
ALTMEMPHY variation when
dynamic OCT is enabled.
Generates the proper delay and duration for the
OCT signals.
<variation_name>
_alt_mem_phy_po
stamble
DDR2/DDR SDRAM
ALTMEMPHY variations
Generates the postamble enable and disable
scheme for DDR and DDR2 SDRAM PHYs.
<variation_name>
_alt_mem_phy_re
ad_dp
All ALTMEMPHY variations
(unused for Stratix III or
Stratix IV devices)
Takes read data from the I/O through a read path
FIFO buffer, to transition from the
resyncronization clock to the PHY clock.
<variation_name>
_alt_mem_phy_re
ad_dp_group
DDR2/DDR SDRAM
ALTMEMPHY variations
(Stratix III and Stratix IV
devices only)
A per DQS group version of
<variation_name>
_alt_mem_phy_read_dp
.
<variation_name>
_alt_mem_phy_rd
ata_valid
DDR2/DDR SDRAM
ALTMEMPHY variations
Generates read data valid signal to sequencer and
controller.
<variation_name>
_alt_mem_phy_se
q_wrapper
All ALTMEMPHY variations Generates sequencer for DDR and DDR2 SDRAM.
<variation_name>
_alt_mem_phy_wr
ite_dp
All ALTMEMPHY variations
Generates the demultiplexing of data from
half-rate to full-rate DDR data.
<variation_name>
_alt_mem_phy_wr
ite_dp_fr
DDR2/DDR SDRAM
ALTMEMPHY variations
A full-rate version of
<variation_name>
_alt_mem_phy_
write_dp
.
Table 2–4. Modules in <variation_name>_alt_mem_phy.v File (Part 2 of 2)
Module Name Usage Description
Table 2–5. Controller-Generated Files (Part 1 of 2)
Filename Description
alt_mem_ddrx_addr_cmd.v
Decodes internal protocol-related signals into memory address and
command signals.
alt_mem_ddrx_addr_cmd_wrap.v A wrapper that instantiates the alt_mem_ddrx_addr_cmd.v file.
alt_mem_ddrx_ddr2_odt_gen.v
Generates the on-die termination (ODT) control signal for DDR2
memory interfaces.
alt_mem_ddrx_ddr3_odt_gen.v
Generates the on-die termination (ODT) control signal for DDR3
memory interfaces.
alt_mem_ddrx_odt_gen.v
Wrapper that instantiates alt_mem_ddrx_ddr2_odt_gen.v and
alt_mem_ddrx_ddr3_odt_gen.v. This file also controls the ODT
addressing scheme.
alt_mem_ddrx_rdwr_data_tmg.v Decodes internal data burst related signals to memory data signals.
alt_mem_ddrx_arbiter.v
Contains logic that determines which command to execute based on
certain schemes.
alt_mem_ddrx_burst_gen.v Converts internal DRAM-aware commands to AFI signals.
alt_mem_ddrx_cmd_gen.v Converts user requests to DRAM-aware commands.
alt_mem_ddrx_csr.v Contains configuration registers.
alt_mem_ddrx_buffer.v Contains buffer for local data.
alt_mem_ddrx_buffer_manager.v Manages the allocation of buffers.
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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